Datasheet

RL78/L12 CHAPTER 3 CPU ARCHITECTURE
R01UH0330EJ0200 Rev.2.00 54
Dec 13, 2013
Figure 3-2. Memory Map (R5F10RxA (x = B, F, G, J, L))
00000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
F3FFFH
F4000H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
03FFFH
03FFFH
04000H
Special function register (SFR)
256 bytes
RAM
Notes 1, 2
1 KB
General-purpose register
32 bytes
Special function register (2nd SFR)
2 KB
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 3
4 bytes
Reserved
Reserved
FFAFFH
FFB00H
Mirror
8 KB
Reserved
Reserved
Program area
Code flash memory
16 KB
Program area
Program
memory
space
Data memory
space
On-chip debug security
ID setting area
Note 3
10 bytes
000CDH
000CEH
Data flash memory
2 KB
F17FFH
F1800H
F1FFFH
F2000H
Boot
cluster 0
Note 4
Notes 1. Use of the area FFE20H to FFEDFH and FFB00H to FFC89H is prohibited when using the self-
programming function and data flash function, because this area is used for self-programming library.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Settings).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively.
Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see
23.3.3 RAM parity error detection function.