Datasheet

RL78/L12 CHAPTER 19 STANDBY FUNCTION
R01UH0330EJ0200 Rev.2.00 735
Dec 13, 2013
Table 19-1. Operating Statuses in HALT Mode (2/2)
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH: High-speed on-chip oscillator clock fEX: External main system clock
fIL: Low-speed on-chip oscillator clock fXT: XT1 clock
fX: X1 clock fEXS: External subsystem clock
HALT Mode Setting
Item
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
When CPU Is Operating on XT1 Clock (fXT) When CPU Is Operating on External
Subsystem Clock (f
EXS)
System clock Clock supply to the CPU is stopped
Main system clock fIH Operation disabled
fX
fEX
Subsystem clock fXT Operation continues (cannot be stopped) Cannot operate
fEXS Cannot operate Operation continues (cannot be stopped)
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM
Port (latch) Status before HALT mode was set is retained
Timer array unit Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Real-time clock (RTC) Operable
12-bit interval timer
Watchdog timer See CHAPTER 10 WATCHDOG TIMER
Clock output/buzzer output Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
A/D converter Operation disabled
Serial array unit (SAU) Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Serial interface (IICA) Operation disabled
LCD driver/controller Operable (However, this depends on the status of the clock selected as the LCD source clock:
operation is possible if the selected clock is operating, but operation will stop if the selected
clock is stopped.)
Multiplier and divider/multiply-
accumulator
Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
DMA controller
Power-on-reset function Operable
Voltage detection function
External interrupt
Key interrupt function
CRC
operation
function
High-speed CRC Operation disabled
General-purpose
CRC
In the calculation of the RAM area, operable when DMA is executed only
RAM parity error detection
function
Operable when DMA is executed only
RAM guard function
SFR guard function
Illegal-memory access detection
function
Operation stopped