Datasheet

RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0330EJ0200 Rev.2.00 702
Dec 13, 2013
Table 17-1. Interrupt Source List (3/3)
Interrupt
Type
Default Priority
Note 1
Interrupt Source
Internal/
External
Vector
Table
Address
Basic Configuration Type
Note 2
64-pin 52-pin 48-pin 44-pin 32-pin
Software − BRK Execution of BRK instruction − 007EH (D) √ √ √ √ √
Reset − RESET RESET pin input − 0000H − √ √ √ √ √
POR Power-on-reset √ √ √ √ √
LVD Voltage detection
Note 3
√ √ √ √ √
WDT Overflow of watchdog timer √ √ √ √ √
TRAP Execution of illegal instruction
Note 4
√ √ √ √ √
IAW Illegal-memory access √ √ √ √ √
RPE RAM parity error √ √ √ √ √
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 31 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
3. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is set to 1.
4. When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Remark √: Mounted