Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 623
Dec 13, 2013
• P13, P14, P41, P120, P142 to P147 (ports that serve as analog input pins (ANIxx))
Table 14-9. Settings of ANIxx/SEGxx/Port Pin Function
PMCxx Bit of
PMCxx Register
PFSEGxx Bit
PFSEG0 to PFSEG4 Registers
PMxx Bit of
PMxx Register
Pin Function Initial Status
1 1 1 Analog input mode
√
0 0 0 Digital output mode
−
0 0 1 Digital input mode
−
0 1 0 Segment output mode
−
0 1 1 Digital input ineffective mode
−
Other than above
Setting prohibited
The following shows the ANIxx/SEGxx/port pin function status transitions.
Figure 14-13. ANIxx/SEGxx/Port Pin Function Status Transitions
Reset status
Reset release
PFSEGxx = 0
PMmn = 0
PMmn = 0
PMCmn = 0
PMmn = 1
Digital input
ineffective mode
Analog input
mode
Digital input
mode
Digital output
mode
Segment
output mode
Caution Be sure to set the segment output mode before segment output starts (while SCOC bit of
LCD mode register 1 (LCDM1) is 0).