Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 503
Dec 13, 2013
Table 12-4. Selection of Operation Clock For UART
SMRmn
Register
SPSm Register Operation Clock (fMCK)
Note
CKSmn PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
fCLK = 24 MHz
0 X X X X 0 0 0 0 fCLK 24 MHz
X X X X 0 0 0 1 fCLK/2 12 MHz
X X X X 0 0 1 0 fCLK/2
2
6 MHz
X X X X 0 0 1 1 fCLK/2
3
3 MHz
X X X X 0 1 0 0 fCLK/2
4
1.5 MHz
X X X X 0 1 0 1 fCLK/2
5
750 kHz
X X X X 0 1 1 0 fCLK/2
6
375 kHz
X X X X 0 1 1 1 fCLK/2
7
187.5 kHz
X X X X 1 0 0 0 fCLK/2
8
93.8 kHz
X X X X 1 0 0 1 fCLK/2
9
46.9 kHz
X X X X 1 0 1 0 fCLK/2
10
23.4 kHz
X X X X 1 0 1 1 fCLK/2
11
11.7 kHz
X X X X 1 1 0 0 fCLK/2
12
5.86 kHz
X X X X 1 1 0 1 fCLK/2
13
2.93 kHz
X X X X 1 1 1 0 fCLK/2
14
1.46 kHz
X X X X 1 1 1 1 fCLK/2
15
732 Hz
1 0 0 0 0 X X X X fCLK 24 MHz
0 0 0 1 X X X X fCLK/2 12 MHz
0 0 1 0 X X X X fCLK/2
2
6 MHz
0 0 1 1 X X X X fCLK/2
3
3 MHz
0 1 0 0 X X X X fCLK/2
4
1.5 MHz
0 1 0 1 X X X X fCLK/2
5
750 kHz
0 1 1 0 X X X X fCLK/2
6
375 kHz
0 1 1 1 X X X X fCLK/2
7
187.5 kHz
1 0 0 0 X X X X fCLK/2
8
93.8 kHz
1 0 0 1 X X X X fCLK/2
9
46.9 kHz
1 0 1 0 X X X X fCLK/2
10
23.4 kHz
1 0 1 1 X X X X fCLK/2
11
11.7 kHz
1 1 0 0 X X X X fCLK/2
12
5.86 kHz
1 1 0 1 X X X X fCLK/2
13
2.93 kHz
1 1 1 0 X X X X fCLK/2
14
1.46 kHz
1 1 1 1 X X X X fCLK/2
15
732 Hz
Other than above Setting prohibited
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remarks 1. X: Don’t care
2. m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01