Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 501
Dec 13, 2013
Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1,
FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore,
when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting
the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9
bits).
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-91 Timing Chart of SNOOZE
Mode Operation (EOCm1 = 1, SSECm = 1).
2. m = 0; q = 0