Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 397
Dec 13, 2013
Figure 12-9. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
TSF
mn
BFF
mn
0 0
FEF
mn
Note
PEF
mn
OVF
mn
FEF
mn
Note
Framing error detection flag of channel n
0
No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
• 1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
• A stop bit is not detected when UART reception ends.
PEF
mn
Parity error detection flag of channel n
0 No error occurs.
1 Parity error occurs (during UART reception).
<Clear condition>
• 1 is written to the PECTmn bit of the SIRmn register.
<Set condition>
• The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
OVF
mn
Overrun error detection flag of channel n
0 No error occurs.
1 An error occurs
<Clear condition>
• 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
• Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
• Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Note The SSR01 register only.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1)