Datasheet
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 389
Dec 13, 2013
12.3.2 Serial clock select register m (SPSm)
The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits
3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears the SPSm register to 0000H.
Figure 12-4. Format of Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPSm 0 0 0 0 0 0 0 0
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
PRS
mk3
PRS
mk2
PRS
mk1
PRS
mk0
Section of operation clock (CKmk)
Note 1
fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 24 MHz
0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz 12 MHz
0 0 1 0 fCLK/2
2
500 kHz 1.25 MHz 2.5 MHz 5 MHz 6 MHz
0 0 1 1 fCLK/2
3
250 kHz 625 kHz 1.25 MHz 2.5 MHz 3 MHz
0 1 0 0 fCLK/2
4
125 kHz 313 kHz 625 kHz 1.25 MHz 1.5 MHz
0 1 0 1 fCLK/2
5
62.5 kHz 156 kHz 313 kHz 625 kHz 750 kHz
0 1 1 0 fCLK/2
6
31.3 kHz 78.1 kHz 156 kHz 313 kHz 375 kHz
0 1 1 1 fCLK/2
7
15.6 kHz 39.1 kHz 78.1 kHz 156 kHz 187.5 kHz
1 0 0 0 fCLK/2
8
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 93.8 kHz
1 0 0 1 fCLK/2
9
3.91 kHz 9.77 kHz 19.5 kHz 39.1 kHz 46.9 kHz
1 0 1 0 fCLK/2
10
1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz 23.4 kHz
1 0 1 1 fCLK/2
11
977 Hz 2.44 kHz 4.88 kHz 9.77 kHz 11.7 kHz
1 1 0 0 fCLK/2
12
488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 5.86 kHz
1 1 0 1 fCLK/2
13
244 Hz 610 Hz 1.22 kHz 2.44 kHz 2.93 kHz
1 1 1 0 fCLK/2
14
122 Hz 305 Hz 610 Hz 1.22 kHz 1.46 kHz
1 1 1 1 fCLK/2
15
61 Hz 153 kHz 305 Hz 610 Hz 732 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of
the serial array unit (SAU).
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
f
SUB: Subsystem clock frequency
2. m: Unit number (m = 0)
3. k = 0, 1