Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 374
Dec 13, 2013
(3) Operation when A/D conversion is interrupted or resumed
If A/D conversion is interrupted (by clearing bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0), the clock
request signal (an internal signal) is set to the low level, and supplying the high-speed on-chip oscillator clock stops.
When another hardware trigger is input, the clock request signal is set to the high level, supplying the high-speed on-
chip oscillator clock resumes, and A/D conversion starts in the SNOOZE mode.
Figure 11-31. Example of Operation When A/D Conversion Is Interrupted or Resumed
Conversion is
interrupted.
If ADCS is cleared to 0 during A/D
conversion, the clock request
signal is also set to the low level.
When the hardware clock is input again, the clock request signal
is set to the high level, and the clock is supplied.
ADCS
Interrupt signal
(INTAD)
INTRTC
Clock request signal
(internal signal)
Conversion
status
Conversion standby
Channel 1
Conversion standby
Channel 1