Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 339
Dec 13, 2013
11.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> 3 <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
ADCEN Control of A/D converter input clock supply
0
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Cautions 1. When setting the A/D converter, be sure to set the following registers first while the
ADCEN bit is set to 1. If ADCEN = 0, writing to a control register of the A/D converter is
ignored, and, even if the register is read, only the default value is read (except for port
mode registers 1, 2, 4, 12, and 14 (PM1, PM2, PM4, PM12, and PM14), port mode registers
1, 2, 4, 12, and 14 (PM1, PM2, PM4, PM12, and PM14), port mode control registers 1, 4, 12,
and 14 (PMC1, PMC4, PMC12, PMC14), and A/D port configuration register (ADPC)).
• A/D converter mode register 0 (ADM0)
• A/D converter mode register 1 (ADM1)
• A/D converter mode register 2 (ADM2)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
• Analog input channel specification register (ADS)
• Conversion result comparison upper limit setting register (ADUL)
• Conversion result comparison lower limit setting register (ADLL)
• A/D test register (ADTES).
2. Be sure to clear bits 1, 3, and 6 to 0.