Datasheet
RL78/L12 CHAPTER 1 OUTLINE
R01UH0330EJ0200 Rev.2.00 10
Dec 13, 2013
• 64-pin plastic LQFP (fine pitch) (10 × 10)
• 64-pin plastic LQFP (12 × 12)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/V
L3
V
L4
V
L2
V
L1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
EV
SS
V
DD
EV
DD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Cautions 1. Make EV
SS pin the same potential as VSS pin.
2. Make V
DD pin the same potential as EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the V
DD and EVDD pins and connect
the V
SS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
<R>
<R>