Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 282
Dec 13, 2013
Figure 6-85. Procedure for Setting Remote Control Output (1/2)
Software Operation Hardware Status
Pin mode
setting
Sets the PFSEG17 bit of PFSEG2 register, PM32 bit of
PM3 register, PU3 bit of PFSEG2 register and P32 bit of
P3 register to 1
Remote control output is invaild
P32/TO03 pin is low-level output
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Remote
control
output
setting
The TOS0 bit of the Timer output select register (TOS) is
set to 1. Remote control output is valid
The P32/TO03 pin outputs the result (Low) of ANDing
TO03 (Low) and TO07 (Low).
P32/TO03 pin can only be used as a remote control
output
P53/TO07 pin can only be used as a alternative
function other than timer output
Channel
default
setting
Sets timer mode register mn (TMRmn) to 0801H and
sets timer mode register mp (TMRmp) to 0409H
determines operation mode of channels)..
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets master channels.
The TOMmn bit of timer output mode register m
(TOMm) is set to 0 (master channel output mode).
Sets the TOLmn bit.
Sets the TOmn bit and determines default level of the
TOmn output.
Sets the TOEmn bit to 1 and enables operation of
TOmn.
Clears the port register and port mode register to 0.
The TOmn pin goes into Hi-Z output state.
The TOmn default setting level is output when the port
mode register is in output mode and the port register is 0.
TOmn does not change because channels stop operating.
The TOmn pin outputs the TOmn set level.
Sets slave channels.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
Sets the TOEmp bit to 1 and enables operation of
TOmp.
Clears the port register and port mode register to 0.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
TOmp does not change because channels stop operating.
The TOmp pin outputs the TOmp set level.
(Remark is listed on the next page.)