Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 182
Dec 13, 2013
Figure 6-6. Internal Block Diagram of Channel 7 of Timer Array Unit 0
TO07
PMxx
CKS07 CCS07STS072STS071 STS070 MD072CIS071CIS070 MD073 MD071MD070
OVF
07
INTTM07
(Timer interrupt)
CK00
CK01
f MCK
f TCLK
TI07
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 07 (TSR07)
Overflow
Timer data register 07 (TDR07)
Timer counter register 07 (TCR07)
Timer mode register 07 (TMR07)
Channel 7
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Edge
detection
Operating
clock selection
Input signal from the master channel
6.2.1 Timer count register mn (TCRmn)
The TCRmn register is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to
MDmn0 bits of timer mode register mn (TMRmn) (refer to 6.3.3 Timer mode register mn (TMRmn)).
Figure 6-7. Format of Timer Count Register mn (TCRmn)
Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07) After reset: FFFFH R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRmn
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
F0181H (TCR00)
F0180H (TCR00)
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