Datasheet

Index-11
15.3.1 Multiplication/division control register (MDUC) ............................................................................. 668
15.4 Operations of Multiplier and Divider/Multiply-Accumulator ................................................ 670
15.4.1 Multiplication (unsigned) operation ............................................................................................... 670
15.4.2 Multiplication (signed) operation ................................................................................................... 671
15.4.3 Multiply-accumulation (unsigned) operation ................................................................................. 672
15.4.4 Multiply-accumulation (signed) operation ..................................................................................... 674
15.4.5 Division operation ......................................................................................................................... 676
CHAPTER 16 DMA CONTROLLER ..................................................................................................... 678
16.1 Functions of DMA Controller .................................................................................................. 678
16.2 Configuration of DMA Controller ............................................................................................ 679
16.2.1 DMA SFR address register n (DSAn) ........................................................................................... 679
16.2.2 DMA RAM address register n (DRAn) .......................................................................................... 680
16.2.3 DMA byte count register n (DBCn) ............................................................................................... 681
16.3 Registers Controlling DMA Controller ................................................................................... 682
16.3.1 DMA mode control register n (DMCn) .......................................................................................... 683
16.3.2 DMA operation control register n (DRCn) ..................................................................................... 685
16.4 Operation of DMA Controller ................................................................................................... 686
16.4.1 Operation procedure .................................................................................................................... 686
16.4.2 Transfer mode .............................................................................................................................. 687
16.4.3 Termination of DMA transfer ........................................................................................................ 687
16.5 Example of Setting of DMA Controller ................................................................................... 688
16.5.1 CSI consecutive transmission ...................................................................................................... 688
16.5.2 Consecutive capturing of A/D conversion results ......................................................................... 690
16.5.3 UART consecutive reception + ACK transmission........................................................................ 692
16.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 694
16.5.5 Forced termination by software .................................................................................................... 695
16.6 Cautions on Using DMA Controller ........................................................................................ 697
CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................. 699
17.1 Interrupt Function Types ......................................................................................................... 699
17.2 Interrupt Sources and Configuration ..................................................................................... 699
17.3 Registers Controlling Interrupt Functions ............................................................................. 705
17.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L) ..................................................... 708
17.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L) .............................................. 710
17.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L,
PR10L, PR10H, PR11L, PR11H, PR12L) .................................................................................... 711
17.3.4 External interrupt rising edge enable register (EGP0),
external interrupt falling edge enable register (EGN0) ................................................................. 713
17.3.5 Program status word (PSW) ......................................................................................................... 715
17.4 Interrupt Servicing Operations ............................................................................................... 716