Datasheet

RL78/L12 CHAPTER 5 CLOCK GENERATOR
R01UH0330EJ0200 Rev.2.00 143
Dec 13, 2013
5.3.6 Peripheral enable register 0 (PER0)
These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
• Real-time clock, 12-bit interval timer
• A/D converter
• Serial interface IICA0
• Serial array unit 0
• Timer array unit 0
• LCD driver/controller
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/2)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> 3 <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
RTCEN
Real-time clock (RTC) and
12-bit interval timer
LCD driver/controller and clock output/buzzer output controller
When subsystem clock (fSUB)
is selected.
When subsystem clock (fSUB)
is not selected.
0
Stops input clock supply.
• SFR used by the real-time
clock (RTC) and 12-bit
interval timer cannot be
written.
• The real-time clock (RTC)
and 12-bit interval timer
are in the reset status.
Stops input clock and
subsystem clock supply.
• SFR used by the LCD
driver/controller and clock
output/buzzer output can
be read and written.
Enables input clock and
main system clock supply.
• SFR used by the LCD
driver/controller and clock
output/buzzer output can
be read and written.
1
Enables input clock supply.
• SFR used by the real-time
clock (RTC) and 12-bit
interval timer can be read
and written.
Enables input clock and
subsystem clock supply.
• SFR used by the LCD
driver/controller and clock
output/buzzer output can
be read and written.
ADCEN Control of A/D converter input clock supply
0
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read and written.
Caution Be sure to clear the following bits 1, 3, and 6 to 0.