Datasheet

RL78/L12 CHAPTER 5 CLOCK GENERATOR
R01UH0330EJ0200 Rev.2.00 130
Dec 13, 2013
CHAPTER 5 CLOCK GENERATOR
The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem
clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the
product.
Output pin 32-pin 44, 48, 52, 64-pin
X1, X2 pins
√ √
EXCLK pin
√ √
XT1, XT2 pins
− √
EXCLKS pin
− √
Caution The 32-pin products don’t have the subsystem clock.
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of f
X = 1 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
<2> High-speed on-chip oscillator
The frequency at which to oscillate can be selected from among f
IH = 24, 16, 12, 8, 4, or 1 MHz (typ.) by using
the option byte (000C2H). After a reset release, the CPU always starts operating with this high-speed on-
chip oscillator clock. Oscillation can be stopped by executing the STOP instruction or setting the HIOSTOP
bit (bit 0 of the CSC register).
The frequency specified by using an option byte can be changed by using the high-speed on-chip oscillator
frequency select register (HOCODIV). For details about the frequency, see Figure 5-9 Format of High-
speed On-chip Oscillator Frequency Select Register (HOCODIV).
The frequencies that can be specified for the high-speed on-chip oscillator by using the option byte and the
high-speed on-chip oscillator frequency select register (HOCODIV) are shown below.
Power Supply Voltage Oscillation Frequency (MHz)
1 2 3 4 6 8 12 16 24
2.7 V ≤ VDD ≤ 5.5 V
√ √ √ √ √ √ √ √ √
2.4 V ≤ VDD < 2.7 V
√ √ √ √ √ √ √ √ −
1.8 V ≤ VDD < 2.4 V
√ √ √ √ √ √ − − −
1.6 V ≤ VDD < 1.8 V
√ √ − √ − − − − −