User’s Manual 16 RL78/L12 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.
Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.
NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/L12 and design and develop application systems and programs for these devices. The target products are as follows.
Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...×××× or ××××B Numerical representations: Binary ...×××× Decimal Hexadecimal Related Documents ...××××H The related documents indicated in this publication may include preliminary versions.
Other Documents Document Name Renesas MPUs & MCUs RL78 Family Document No. R01CP0003E Semiconductor Package Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Semiconductor Reliability Handbook R51ZZ0001E Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp).
CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Features ........................................................................................................................................... 1 1.2 List of Part Numbers ...................................................................................................................... 3 1.3 Pin Configuration (Top View) .....................
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 62 3.1.6 Data memory addressing ................................................................................................................. 63 3.2 Processor Registers..................................................................................................................... 64 3.2.1 Control registers ...................................................................................
4.3.4 Port input mode register (PIM1) ..................................................................................................... 109 4.3.5 Port output mode register (POM1) ................................................................................................. 109 4.3.6 Port mode control registers (PMCxx) ............................................................................................. 110 4.3.7 A/D port configuration register (ADPC) ..........................................
5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 155 5.6.2 Example of setting X1 oscillation clock ........................................................................................... 156 5.6.3 Example of setting XT1 oscillation clock ........................................................................................ 157 5.6.4 CPU clock status transition diagram .....................................................
6.5.3 Operation of counter ....................................................................................................................... 215 6.6 Channel Output (TOmn pin) Control ........................................................................................ 220 6.6.1 TOmn pin output circuit configuration ............................................................................................. 220 6.6.2 TOmn Pin Output Setting .........................................................
7.3.14 Alarm hour register (ALARMWH) ................................................................................................. 300 7.3.15 Alarm week register (ALARMWW) ............................................................................................... 300 7.3.16 Port mode register 3 (PM3) .......................................................................................................... 301 7.3.17 Port register 3 (P3) ...............................................................
10.4.1 Controlling operation of watchdog timer ....................................................................................... 330 10.4.2 Setting overflow time of watchdog timer ....................................................................................... 331 10.4.3 Setting window open period of watchdog timer ............................................................................ 332 10.4.4 Setting watchdog timer interval interrupt ....................................................
CHAPTER 12 SERIAL ARRAY UNIT .................................................................................................. 381 12.1 Functions of Serial Array Unit................................................................................................. 381 12.1.1 3-wire serial I/O (CSI00, CSI01) ................................................................................................... 381 12.1.2 UART (UART0) ...............................................................................
12.6.2 UART reception ............................................................................................................................ 487 12.6.3 SNOOZE mode function ............................................................................................................... 494 12.6.4 Calculating baud rate ................................................................................................................... 502 12.6.
13.6 Timing Charts ........................................................................................................................... 586 CHAPTER 14 LCD CONTROLLER/DRIVER ....................................................................................... 601 14.1 Functions of LCD Controller/Driver ........................................................................................ 603 14.2 Configuration of LCD Controller/Driver ...............................................................
15.3.1 Multiplication/division control register (MDUC) ............................................................................. 668 15.4 Operations of Multiplier and Divider/Multiply-Accumulator ................................................ 670 15.4.1 Multiplication (unsigned) operation ............................................................................................... 670 15.4.2 Multiplication (signed) operation ..........................................................................
17.4.1 Maskable interrupt request acknowledgment ............................................................................... 716 17.4.2 Software interrupt request acknowledgment ................................................................................ 719 17.4.3 Multiple interrupt servicing ............................................................................................................ 719 17.4.4 Interrupt request hold ..................................................................
22.3 Registers Controlling Voltage Detector ................................................................................. 760 22.3.1 Voltage detection register (LVIM) ................................................................................................. 761 22.3.2 Voltage detection level register (LVIS) ......................................................................................... 762 22.4 Operation of Voltage Detector ..............................................................
25.4 Setting of Option Byte.............................................................................................................. 804 CHAPTER 26 FLASH MEMORY .......................................................................................................... 805 26.1 Writing to Flash Memory by Using Flash Memory Programmer ......................................... 807 26.1.1 Programming Environment ................................................................................................
28.3 BCD Correction Circuit Operation .......................................................................................... 831 CHAPTER 29 INSTRUCTION SET........................................................................................................ 833 29.1 Conventions Used in Operation List ...................................................................................... 834 29.1.1 Operand identifiers and specification methods ............................................................
31.2 Oscillator Characteristics ........................................................................................................ 917 31.2.1 X1, XT1 oscillator characteristics ................................................................................................. 917 31.2.2 On-chip oscillator characteristics .................................................................................................. 918 31.3 DC Characteristics .........................................................
R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 RL78/L12 RENESAS MCU CHAPTER 1 OUTLINE 1.1 Features Ultra-low power consumption technology • VDD = single power supply voltage of 1.6 to 5.5 V which can operate a 1.8 V device at a low voltage • HALT mode • STOP mode • SNOOZE mode RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high speed (0.04167 μs: @ 24 MHz operation with highspeed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.
RL78/L12 CHAPTER 1 OUTLINE DMA (Direct Memory Access) controller • 2 channels • Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks Multiplier and divider/multiply-accumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) LCD controller/driver (internal voltage boosting method (44-, 48-, 52-, 64-pin products only), capacitor split method, and external resistance division
RL78/L12 CHAPTER 1 OUTLINE ROM, RAM capacities Flash ROM Data flash 32 KB 16 KB 8KB Note 2 KB 2 KB 2 KB RAM Note 1.5 KB 1 KB 1 KB Note Note RL78/L12 32 pins 44 pins 48 pins 52 pins 64 pins R5F10RBC R5F10RFC R5F10RGC R5F10RJC R5F10RLC R5F10RBA R5F10RFA R5F10RGA R5F10RJA R5F10RLA R5F10RB8 R5F10RF8 R5F10RG8 R5F10RJ8 − In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash function is used.
RL78/L12 CHAPTER 1 OUTLINE Pin count Package Application 32 pins 44 pins 48 pins 52 pins 64 pins 32-pin plastic LQFP (7 × 7) Part Number Fields of Note A R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP G R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP A R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP G R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP 48-pin plastic LQFP A R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB (fine pitch) (7 × 7) G R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB 52-pin plastic LQFP (10 × 10) A R5F10RJ8AFA, R
RL78/L12 CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.
RL78/L12 CHAPTER 1 OUTLINE 1.3.
RL78/L12 CHAPTER 1 OUTLINE 1.3.
RL78/L12 CHAPTER 1 OUTLINE 1.3.
RL78/L12 CHAPTER 1 OUTLINE 1.3.
RL78/L12 CHAPTER 1 OUTLINE • 64-pin plastic LQFP (fine pitch) (10 × 10) • 64-pin plastic LQFP (12 × 12) COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P15/SCK01/INTP1/SEG4 P16/SI01/INTP2/SEG5 P17/SO01/TI02/TO02/SEG6 P50/INTP5/SEG7/(PCLBUZ0) P51/TI06/TO06/SEG8 P52/INTP6/SEG9 P53/TI07/TO07/SEG10/(INTP1) P54/SEG11/(TI02)/(TO02)/(INTP2) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P147/SEG38 P146/SEG37 P145/ANI23/SEG36 P144/ANI22/SEG35 P143/ANI2
RL78/L12 CHAPTER 1 OUTLINE 1.
RL78/L12 CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.
RL78/L12 CHAPTER 1 OUTLINE 1.5.
RL78/L12 CHAPTER 1 OUTLINE 1.5.
RL78/L12 CHAPTER 1 OUTLINE 1.5.
RL78/L12 CHAPTER 1 OUTLINE 1.5.
RL78/L12 CHAPTER 1 OUTLINE 1.6 Outline of Functions Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item Code flash memory (KB) 32-pin 44-pin 48-pin 52-pin 64-pin R5F10RBx R5F10RFx R5F10RGx R5F10RJx R5F10RLx 8 to 32 8 to 32 8 to 32 8 to 32 16, 32 Data flash memory (KB) RAM (KB) Memory space Main system clock 2 1, 1.5 Note 1 2 1, 1.5 Note 1 2 1, 1.5 2 Note 1 1, 1.5 Note 1 2 1, 1.
RL78/L12 CHAPTER 1 OUTLINE (2/2) Item Timer 16-bit timer 32-pin 44-pin 48-pin 52-pin 64-pin R5F10RBx R5F10RFx R5F10RGx R5F10RJx R5F10RLx 8 channels 8 channels (with 1 channel remote control output function) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer (IT) 1 channel Timer output RTC output Clock output/buzzer output 4 channels 5 channels 6 channels 8 channels (PWM outputs: 7 (PWM outputs: (PWM outputs: (PWM outputs: Note 1 Note 1 Note 1 3 ) 4 )
RL78/L12 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Function Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 2-1.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions. 2.1.1 32-pin products (1/2) Function Pin Type I/O After Reset Alternate Function Function Name P10 8-5-7 P11 I/O Digital input SCK00/TI07/TO07/ Port 1. invalid KR2/SEG28/ 8-bit I/O port. (INTP1) Input/output can be specified in 1-bit units. SI00/RxD0/ Use of an on-chip pull-up resistor can be specified by a TOOLRxD/KR1/ software setting at input port.
RL78/L12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type I/O After Reset Alternate Function Function Name P60 12-1-4 I/O P61 Digital input SCLA0/SEG21 Port 6. invalid SDAA0/SEG20 2-bit I/O port. Input/output can be specified in 1-bit units. P121 2-2-1 Input Input port P122 X1 Port 12. X2/EXCLK 2-bit I/O port and 2-bit input port. For P126 and P127, input/output can be specified in 1- P126 8-5-2 I/O P127 Digital input CAPL invalid CAPH bit units.
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.1.2 44-pin products (1/2) Function Pin Type I/O After Reset Alternate Function Function Name P10 8-5-7 P11 I/O Digital input SCK00/TI07/TO07/ Port 1. invalid KR2/SEG28/ 8-bit I/O port. (INTP1) Input/output can be specified in 1-bit units. SI00/RxD0/TOOLRxD/ Use of an on-chip pull-up resistor can be specified by KR1/SEG29/ a software setting at input port. 8-5-1 (INTP2) P12 7-5-7 input buffer.
RL78/L12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type I/O After Reset Alternate Function Function Name P60 12-1-4 I/O P61 Digital input SCLA0/SEG21 Port 6. invalid SDAA0/SEG20 2-bit I/O port. Input/output can be specified in 1-bit units. P120 7-10-1 I/O Analog input port ANI17/SEG25 Port 12. P121 2-2-1 Input Input port 4-bit I/O port and 4-bit input port.
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.1.3 48-pin products (1/2) Function Pin Type I/O After Reset Alternate Function Function Name Digital input SCK00/TI07/TO07/ Port 1. invalid SEG28/ 8-bit I/O port. (INTP1) Input/output can be specified in 1-bit units. SI00/RxD0/ Use of an on-chip pull-up resistor can be specified TOOLRxD/SEG29/ by a software setting at input port. (INTP2) Input of P10, P11, P15, and P16 can be set to TTL SO00/TxD0/ input buffer.
RL78/L12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type I/O After Reset Alternate Function Function Name P50 7-5-1 I/O Digital input INTP5/SEG7/ Port 5. invalid (PCLBUZ0) 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 12-1-4 I/O P61 Digital input SCLA0/SEG21 Port 6. invalid SDAA0/SEG20 2-bit I/O port. Input/output can be specified in 1-bit units.
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.1.4 52-pin products (1/2) Function Pin Type I/O After Reset Alternate Function Function Name P10 8-5-7 P11 I/O Digital input SCK00/ Port 1. invalid TI07/TO07/SEG28/ 8-bit I/O port. (INTP1) Input/output can be specified in 1-bit units. SI00/RxD0/ Use of an on-chip pull-up resistor can be specified TOOLRxD/SEG29/ by a software setting at input port.
RL78/L12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type I/O After Reset Alternate Function Function Name P50 7-5-1 I/O Digital input INTP5/SEG7/ Port 5. invalid (PCLBUZ0) 2-bit I/O port. TI06/TO06/SEG8 Input/output can be specified in 1-bit units. P51 Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 12-1-4 I/O P61 Digital input SCLA0/SEG21 Port 6. invalid SDAA0/SEG20 2-bit I/O port. Input/output can be specified in 1-bit units.
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.1.5 64-pin products (1/2) Function Pin Type I/O After Reset Alternate Function Function Name P10 P11 P12 P13 8-5-7 I/O 8-5-1 SCK00/SEG28 Port 1. invalid SI00/RxD0/ 8-bit I/O port. TOOLRxD/SEG29 Input/output can be specified in 1-bit units. SO00/TxD0/ Use of an on-chip pull-up resistor can be specified by TOOLTxD/SEG30 a software setting at input port.
RL78/L12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type I/O After Reset Alternate Function Function Name P50 7-5-1 I/O Digital input INTP5/SEG7/ Port 5. invalid (PCLBUZ0) 5-bit I/O port. TI06/TO06/ Input/output can be specified in 1-bit units. SEG8 Use of an on-chip pull-up resistor can be specified by a P51 software setting at input port. P52 INTP6/SEG9 P53 TI07/TO07/SEG10/ (INTP1) SEG11/(TI02)/ P54 (TO02)/(INTP2) P60 12-1-4 I/O P61 Digital input SCLA0/SEG21 Port 6.
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.2 Functions Other Than Port Pins 2.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS (2/5) 64- 52- 48- 44- 32- pin pin pin pin pin √ − − − − SEG11 √ − − − − SEG12 √ − − − − SEG13 √ − − − − SEG14 √ − − − − SEG15 √ √ − − − SEG16 √ √ √ − − SEG17 √ √ √ √ − SEG18 √ √ √ √ − SEG19 √ √ √ √ √ SEG20 √ √ √ √ √ SEG21 √ √ √ √ √ SEG22 √ − − − − SEG23 √ √ − − − SEG24 √ √ √ − − SEG25 √ √ √ √ − SEG26 √ √ √ √ − SEG27 √ √ √ √ √ SEG28 √ √ √ √ √ SEG29 √
RL78/L12 CHAPTER 2 PIN FUNCTIONS (3/5) 64- 52- 48- 44- 32- pin pin pin pin pin √ √ √ √ √ INTP1 √ √ √ √ √ INTP2 √ √ √ √ √ INTP3 √ √ √ √ − INTP4 √ √ √ √ − INTP5 √ √ √ − − INTP6 √ − − − − INTP7 √ − − − − √ √ √ √ √ KR1 √ √ √ √ √ KR2 √ √ √ √ √ KR3 √ √ √ √ √ √ √ √ √ √ √ √ √ √ − √ √ √ √ √ Function I/O Function Name INTP0 Input KR0 Input PCLBUZ0 Output External interrupt request input Key interrupt input Cloc
RL78/L12 CHAPTER 2 PIN FUNCTIONS (4/5) 64- 52- 48- 44- 32- pin pin pin pin pin External count clock input to 16-bit timer 00 √ √ √ √ √ TI01 External count clock input to 16-bit timer 01 √ √ √ √ √ TI02 External count clock input to 16-bit timer 02 √ √ √ √ √ TI03 External count clock input to 16-bit timer 03 √ √ √ √ − TI04 External count clock input to 16-bit timer 04 √ √ √ − − TI05 External count clock input to 16-bit timer 05 √ √ − − − TI06 External coun
RL78/L12 CHAPTER 2 PIN FUNCTIONS (5/5) Function I/O Function Name − VDD <32-pin, 44-pin, 48-pin, 52-pin> 64- 52- 48- 44- 32- pin pin pin pin pin √ √ √ √ √ √ − − − − Positive power supply for all pins <64-pin > Positive power supply for P20, P21, P121 to P124, P137 and RESET pin − EVDD <64-pin> Positive power supply for ports (other than P20, P21, P121 to P124, P137) and pins other ports (except for the RESET pin) AVREFP Input A/D converter reference potential (+ side) input
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Function Name I/O ⎯ VDD Function <32-pin, 44-pin, 48-pin, 52-pin> Positive power supply for all pins <64-pin > Positive power supply for P20, P21, P121 to P124, P137 and other than ports ⎯ EVDD <64-pin> Positive power supply for ports (other than P20, P21, P121 to P124, P137) AVREFP Input A/D converter reference voltage (+ side) input AVREFM Input A/D converter reference voltage (− side) input ⎯ VSS <32-pin, 44-pin, 48-pin, 52-pin > Ground potential for all
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.3 Connection of Unused Pins Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins. Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Function. Table 2-3. Connection of Unused Pins (64-pin products) (1/3) Pin Name P10/SCK00/SEG28 I/O I/O Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Table 2-3. Connection of Unused Pins (64-pin products) (2/3) Pin Name P50/INTP5/SEG7/(PCLBUZ0) I/O I/O Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor. P51/TI06/TO06/SEG8 Input: P52/INTP6/SEG9 Output: Leave open. P53/TI07/TO07/SEG10/ (INTP1) Leave open.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Table 2-3. Connection of Unused Pins (64-pin products) (3/3) Pin Name COM0 to COM3 I/O Output Recommended Connection of Unused Pins Leave open. COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 VL1, VL2, VL4 R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS 2.4 Block Diagrams of Pins Figures 2-1 to 2-14 show the block diagrams of the pins described in 2.1.1 32-pin products to 2.1.5 64-pin products. Figure 2-1. Pin Block Diagram for Pin Type 1-1-1 Internal bus RD EVDD WRPORT P-ch Output latch Pmn (Pmn) N-ch EVSS Figure 2-2. Pin Block Diagram for Pin Type 2-1-1 RESET RESET Figure 2-3. Pin Block Diagram for Pin Type 2-1-2 Internal bus Alternate function Remark RD Pmn For alternate functions, see 2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-4. Pin Block Diagram for Pin Type 2-2-1 Clock generator CMC OSCSEL/ OSCSELS Internal bus RD Alternate function P122/X2/EXCLK/Alternate function P124/XT2/EXCLKS/Alternate function CMC EXCLK, OSCSEL/ EXCLKS, OSCSELS N-ch P-ch RD Alternate function P121/X1/Alternate function P123/XT1/Alternate function Remark For alternate functions, see 2.1 Port Function. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-5. Pin Block Diagram for Pin Type 4-3-1 WRADPC 0: Analog input 1: Digital I/O ADPC ADPC3 to ADPC0 RD 1 Internal bus 0 VDD WRPORT Output latch (Pmn) P-ch Pmn WRPM N-ch PM register (PMmn) VSS P-ch A/D converter N-ch R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-6. Pin Block Diagram for Pin Type 7-1-1 EVDD WRPU PU register (PUmn) P-ch Alternate function RD 1 Internal bus 0 WRPORT EVDD Output latch (Pmn) P-ch WRPM Pmn PM register (PMmn) N-ch EVSS Alternate function (SAU) Alternate function (other than SAU) Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-7. Pin Block Diagram for Pin Type 7-5-1 Alternate function WRPU EVDD PU register (PUmn) P-ch RDPORT Internal bus 1 0 WRPORT EVDD Output latch (Pmn) P-ch Pmn WRPM N-ch PM register (PMmn) EVSS WRPFSEG PFSEG register (PFSEGmn) Alternate function (SAU) Alternate function (other than SAU) P-ch LCD controller/driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-8. Pin Block Diagram for Pin Type 7-5-7 Alternate function WRPU EVDD PU register (PUmn ) P-ch RDPORT Internal bus 1 0 WRPORT Output latch (Pmn) EVDD P-ch Pmn WRPM WRPOM WRPFSEG N-ch PM register (PMmn) EVSS POM register (POMmn) PFSEG register (PFSEGmn ) Alternate function (SAU) Alternate function (other than SAU) P-ch LCD controller/driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-9. Pin Block Diagram for Pin Type 7-10-1 Alternate function WRPU EVDD PU register (PUmn) P-ch WRPMC PMC register (PMCmn) RDPORT 1 0 Internal bus WRPORT Output latch (Pmn) EVDD P-ch Pmn WRPM N-ch PM register (PMmn) EVSS WRPFSEG PFSEG register (PFSEGmn) Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-10. Pin Block Diagram for Pin Type 8-5-1 Alternate function WRPU EVDD PU register (PUmn) P-ch WRPIM PMC register (PMCmn) RDPORT Internal bus 1 0 WRPORT TTL Output latch (Pmn) EVDD P-ch Pmn WRPM N-ch PM register (PMmn) EVSS WRPFSEG PFSEG register (PFSEGmn) Alternate function (SAU) Alternate function (other than SAU) P-ch LCD controller/driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-11. Pin Block Diagram for Pin Type 8-5-2 Alternate function WRPU EVDD PU register (PUmn ) P-ch WRISCLCD ISCLCD register (LSCCAP) WRPIM PIM register (PIMmn) RDPORT Internal bus 1 0 WRPORT TTL Output latch (Pmn) EVDD P-ch Pmn WRPM N-ch PM register (PMmn) EVSS WRLCDM0 LCDM0 register (MDSET1, 0) Alternate function (SAU) Alternate function (other than SAU) P-ch LCD controller/ driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-12. Pin Block Diagram for Pin Type 8-5-3 Alternate function WRPU EVDD PU register (PUmn) P-ch WRISCLCD ISCLC D register (LSCVL3) WRPIM PI M register (PIMmn) RDPORT Internal bus 1 0 WRPORT TTL Output latch (Pmn) EVDD P-ch Pmn WRPM N-ch PM register (PMmn) EVSS WRLCDM0 LCDM 0 register (LBAS1,0) Alternate function (SAU) Alternate function (other than SAU) P-ch LCD controller/driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-13. Pin Block Diagram for Pin Type 8-5-7 Alternate function WRPU EVDD PU register (PUmn ) P-ch WRPIM PIM register (PIMmn) RDPORT Internal bus 1 0 WRPORT TTL Output latch (Pmn) EVDD P-ch Pmn WRPM N-ch PM register (PMmn) WRPOM EVSS POM register (POMmn) WRPFSEG PFSEG register (PFSEGmn) Alternate function (SAU) P-ch Alternate function (other than SAU) LCD controller/driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function.
RL78/L12 CHAPTER 2 PIN FUNCTIONS Figure 2-14. Pin Block Diagram for Pin Type 12-1-4 Alternate function RDPORT 1 Internal bus 0 WRPORT Output latch (Pmn) WRPM Pmn N-ch PM register (PMmn) VSS Alternate function (SAU) Alternate function (other than SAU) P- ch LCD controller/driver N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/L12 can access a 1 MB address space. Figures 3-1 to 3-3 show the memory maps. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-1.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R5F10RxC (x = B, F, G, J, L)) 07FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH FF900H FF8FFH General-purpose register 32 bytes RAMNotes 1, 2 1.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 07FFFH Block 1FH 07C00H 07BFFH 007FFH 00400H 003FFH Block 01H Block 00H 1 KB 00000H (R5F10RxC (x = B, F, G, J, L)) Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/L12 products incorporate internal ROM (flash memory), as shown below. Table 3-2.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-3.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-3.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/L12 mirrors the code flash area of 02000H to 07FFFH, to F2000H to F7FFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F2000H to F7FFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE • Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 3-4.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/L12 products incorporate the following RAMs. Table 3-4.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/L12, based on operability and other considerations.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/L12 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H, PRn1L, PRn1H, PRn2L) (see 17.3.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-10.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-5.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-5.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-5.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Notes 1. The reset values of the registers vary depending on the reset source as shown below.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-5.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-6.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-6.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-6.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-6.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-6.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Table 3-6.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination. Relative addressing is applied only to branch instructions.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR AX instructions. Figure 3-16.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Implied addressing can be applied only to MULU X. Figure 3-17. Outline of Implied Addressing Instruction code OP code A register Memory (register area) 3.4.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES:!addr16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 3-19.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR SFRP Description SFR name 16-bit-manipulatable SFR name (even address) Figure 3-22. Outline of SFR Addressing Instruction code FFFFFH OP code SFR FFF00H SFR Memory R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description − [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) − ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register) Figure 3-23.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-26. Example of [HL + byte], [DE + byte] [HL + byte], <1> [DE + byte] <1> <2> <2> FFFFFH Instruction code OP-code <2> <2> byte Offset <1> Address of an array rp(HL/DE) Either pair of registers <1> specifies the address where the target array of data starts in the 64-Kbyte area from F0000H to FFFFFH. “byte” <2> specifies an offset within the array to the target location in memory.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-28. Example of word[BC] word [BC] <1> <2> FFFFFH Instruction code <2> <2> OP-code rp(BC) Low Addr. <1> High Addr. <1> Target memory Offset Address of a word within an array “word” <1> specifies the address where the target array of word-sized data starts in the 64-Kbyte area from F0000H to FFFFFH. A pair of registers <2> specifies an offset within the array to the target location in memory. Array of word-sized data F0000H Memory Figure 3-29.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-30. Example of ES:word[B], ES:word[C] ES: word [B], ES: word [C] <1> <2> <3> <1> <2> <3> XFFFFH Instruction code <3> <3> Low Addr. <2> Array of word-sized data Target memory Offset OP-code r(B/C) <2> Address of a word within an array High Addr. X0000H X0000H Specifies a <1> 64-Kbyte area <1> ES The ES register <1> specifies a 64-Kbyte area within the overall Memory 1-Mbyte space as the four higher-order bits, X, of the address range.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Stack addressing is applied only to the internal RAM area.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of POP POP rp <1> <2> <1> Instruction code OP-code <2> SP SP SP+2 SP+1 SP (SP+1) (SP) Stack area F0000H rp Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively. The value of SP <3> is increased by two (if rp is the program status word (PSW), the content of address SP + 1 is stored in the PSW).
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-37. Example of RET RET <1> <1> Instruction code SP OP-code SP SP+4 SP+3 SP+2 SP+1 <3> SP (SP+3) (SP+2) (SP+1) (SP) <2> Stack area F0000H PC Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>. The value of SP <3> is increased by four. Memory Figure 3-38.
RL78/L12 CHAPTER 3 CPU ARCHITECTURE Figure 3-39. Example of RETI, RETB RETI, RETB PSW <1> Instruction code <1> SP OP-code SP SP+4 SP+3 SP+2 SP+1 <3> SP (SP+3) (SP+2) (SP+1) (SP) <2> F0000H PC Stack addressing is specified <1>. The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>. The value of SP <3> is increased by four. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/L12 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-1.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P32 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 12 P120 and P125 to P127 are 4-bit I/O ports with an output latch. These port pins can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). P121 to P124 are 4-bit input-only ports. Digital input/output or analog input can be specified for the P120 pin using port mode control register 12 (PMC12).
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-3.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-3.
RL78/L12 CHAPTER 4 PORT FUNCTIONS For the registers mounted on others than 64-pin products, refer to table 4-3. 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Register Settings When Using Alternate Function. Figure 4-1.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is readNote. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an onchip pull-up resistor has been specified in these registers.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.4 Port input mode register (PIM1) These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication, etc with an external device of the different potential. Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-4.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.6 Port mode control registers (PMCxx) These registers set the P13, P14, P41, P120, and P142 to P145 digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.7 A/D port configuration register (ADPC) This register switches the P20/ANI0, P21/AN21 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-7.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.8 Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. Use the PIOR register to assign a port to the function to redirect and enable the function. In addition, can be changed the settings for redirection until its function enable operation.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.9 LCD port function registers 0 to 4 (PFSEG0 to PFSEG4) These registers set whether to use pins P10 to P17, P30 to P32, P41 to P43, P50 to P54, P60, P61, P70 to P74, P120, and P140 to P147 as port pins (other than segment output pins) or segment output pins. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH (PFSEG0 is set to F0H, and PFSEG4 is set to 7FH).
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-4.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.3.10 LCD input switch control register (ISCLCD) The CAPL/P126, CAPH/P127, and VL3/P125 pins are internally connected with a Schmitt trigger buffer. To use these pins as LCD function, input to the Schmitt trigger buffer must be disabled, in order to prevent through-currents from entering. The ISCLCD register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 4-10.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) It is possible to connect to an external device with a different potential (1.8 V, 2.5 V or 3 V) by changing EVDD to accord with the power supply of the connected device. In products in which EVDD cannot be specified independently, I/O connection with an external device operating on 1.8 V, 2.5 V or 3 V is still possible via the serial interface and generalpurpose port by using port 1.
RL78/L12 CHAPTER 4 PORT FUNCTIONS (2) Setting procedure when using output pins of UART0, CSI00, and CSI01 functions in N-ch open-drain output mode In case of UART0: P12 In case of CSI00: P10, P12 In case of CSI01: P15, P17 <1> Using an external resistor, pull up externally the pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used). <2> After reset release, the port mode is the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.5 Register Settings When Using Alternate Function 4.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog input, use the ADPC register or port mode control register (PMCxx) to specify whether to use the pin for analog input or digital input/output. Figure 4-11 shows the basic configuration of an output circuit for pins used for digital input/output.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-5.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.5.3 Register setting examples for used port and alternate functions Register setting examples for used port and alternate functions are shown in Table 4-6. The registers used to control the port functions should be set as shown in Table 4-6. See the following remark for legends used in Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS Table 4-6.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
RL78/L12 CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple new functions are assigned, the output of the unused alternate function must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR). For details about the alternate output function, see 4.5 Register Settings When Using Alternate Function.
RL78/L12 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the product. Output pin 32-pin 44, 48, 52, 64-pin X1, X2 pins √ √ EXCLK pin √ √ XT1, XT2 pins − √ EXCLKS pin − √ Caution The 32-pin products don’t have the subsystem clock. 5.
RL78/L12 CHAPTER 5 CLOCK GENERATOR An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed onchip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1.
R01UH0330EJ0200 Rev.2.
RL78/L12 Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency fXT: XT1 clock oscillation frequency fEXS: External subsystem clock frequency fSUB: Subsystem clock frequency fCLK: CPU/peripheral hardware clock frequency fIL: Low-speed on-chip oscillator clock frequency 5.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-2.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Cautions 7. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. • Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-3.
RL78/L12 CHAPTER 5 CLOCK GENERATOR the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as CHAPTER 30 or 31 ELECTRICAL SPECIFICATIONS. 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-2. Stopping Clock Method Clock X1 clock External main system clock XT1 clock External subsystem clock High-speed on-chip oscillator clock Condition Before Stopping Clock (Invalidating External Clock Input) CPU and peripheral hardware clocks operate with a clock other than the high-speed system clock. Setting of CSC Register Flags MSTOP = 1 (CLS = 0 and MCS = 0, or CLS = 1) CPU and peripheral hardware clocks operate with a clock other than the subsystem clock.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC After reset: 00H 7 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 8 25.6 μs max. 12.8 μs max. 8 25.6 μs min. 12.8 μs min. 9 51.2 μs min. 25.6 μs min. 10 102.4 μs min. 51.2 μs min.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual operation is automatically delayed for the time set in the OSTS register.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 0 0 0 2 /fX 0 0 1 2 /fX 0 1 0 2 /fX 0 1 1 2 /fX Oscillation stabilization time selection fX = 10 MHz 51.2 μs 25.6 μs 10 102.4 μs 51.2 μs 11 204.8 μs 102.4 μs 13 819.2 μs 409.6 μs 15 3.27 ms 1.64 ms 17 13.11 ms 6.55 ms 18 26.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> 3 <2> 1 <0> PER0 RTCEN 0 ADCEN IICA0EN 0 SAU0EN 0 TAU0EN IICA0EN 0 Control of serial interface IICA0 input clock supply Stops input clock supply. • SFR used by the serial interface IICA0 cannot be written. • The serial interface IICA0 is in the reset status. 1 Enables input clock supply.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.3.7 Subsystem clock supply mode control register (OSMC) This register is used to reduce power consumption by stopping as many unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock, 12-bit interval timer, and LCD driver/controller, is stopped in HALT mode while subsystem clock is selected as CPU clock.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H). The HOCODIV register can be set by an 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted. The HIOTRM register can be set by an 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock VSS XT1 32.768 kHz XT2 Caution External clock EXCLKS When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-13 shows examples of incorrect resonator connection. Figure 5-13. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 NG NG NG (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current (g) Signals are fetched VSS Caution X1 X2 When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/L12. The frequency can be selected from among 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset release. 5.4.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1).
RL78/L12 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply voltage (VDD) 1.6 V 1.51 V (TYP.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 24, 16, 12, 8, 6, 4, 3, 2, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H).
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition (A) → (B) SFR Register Setting SFR registers do not have to be set (default status after reset release).
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-3.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-3.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-3.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-3.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4.
RL78/L12 CHAPTER 5 CLOCK GENERATOR Table 5-4.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the highspeed on-chip oscillator clock and the high-speed system clock).
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-8.
RL78/L12 CHAPTER 5 CLOCK GENERATOR 5.7 Resonator and Oscillator Constants The resonators for which the operation is verified and their oscillator constants are shown below. Cautions 1. The constants for these oscillator circuits are reference values based on specific environments set up for evaluation by the manufacturers. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board.
RL78/L12 CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: As of October, 2013 Manufacturer Resonator Part Number Note 3 SMD/ Frequency Flash Lead (MHz) operation Recommended Circuit Oscillation Voltage Note 2 Range (V) Constants modeNote 1 C1 (pF) Murata Ceramic Manufacturing resonator LV (reference) C2 (pF) Rd (kΩ) MIN. MAX. (47) (47) 0 1.6 5.5 (39) (39) 0 (15) (15) 0 (47) (47) 0 1.8 5.
RL78/L12 CHAPTER 5 CLOCK GENERATOR (2) XT1 oscillation: Crystal resonator As of October, 2013 Manufacturer Note 2 Part Number SMD/ Frequency Load XT1 oscillation mode Recommended Oscillation Note 1 Lead Circuit Voltage Capacitance (kHz) CL (pF) Constants Range (V) C1 C2 Rd MIN. MAX (pF) (pF) (kΩ) Nihon Dempa NX3215SA Note 3 SMD 32.768 6 Kogyo Co., Ltd. Normal oscillation 7 7 Low power 6 7 6 6 0 1.6 5.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit differs, depending on the product. Channels 32-pin 44-pin 48-pin 52-pin 64-pin Channel 0 √ √ √ √ √ Channel 1 √ √ √ √ √ Channel 2 √ √ √ √ √ Channel 3 ⎯ √ √ √ √ Channel 4 ⎯ ⎯ √ √ √ Channel 5 ⎯ ⎯ ⎯ √ √ Channel 6 ⎯ ⎯ ⎯ √ √ Channel 7 √ √ √ √ √ Cautions 1. The presence or absence of timer I/O pins depends on the product.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer. TIMER ARRAY UNIT channel 0 16-bit timers channel 1 channel 2 channel 6 channel 7 For details about each function, see the table below. Independent channel operation function Simultaneous channel operation function • Interval timer (→ refer to 6.8.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels. (1) Interval timer Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.1.3 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3. Caution There are several rules for using 8-bit timer operation function. For details, see 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only). 6.1.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. Table 6-2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-1.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-4.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-6.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT The count value can be read by reading timer count register mn (TCRmn). The count value is set to FFFFH in the following cases.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn). The value of the TDRmn register can be changed at any time. This register can be read or written in 16-bit units.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel from external prescaler. CKm1 is selected by using bits 7 to 4 of the TPSm register, and CKm0 is selected by using bits 3 to 0. In addition, for channel 1 and 3, CKm2 is selected by using bits 9 and 8 of the TPSm register, and CKm3 is selected by using bits 13 and 12.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (fMCK), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B). See Table 6-5 for the operation of the OVF bit in each operation mode and set/clear conditions. The TSRmn register can be read by a 16-bit memory manipulation instruction.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1), because they are trigger bits.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TTHm1, TTHm3 = 0), because they are trigger bits.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 1 timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-17.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel. The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only by the timer operation.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master channel output mode (TOMmn = 0), this register setting is invalid.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using channel 5 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input pin (RxD0) is selected as a timer input signal. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-23.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.15 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is enabled, after synchronization with the operating clock (fMCK) for the target channel, whether the signal keeps the same value for two clock cycles is detected.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-24.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.3.16 Port mode registers 1, 3 to 5, 14 (PM1, PM3 to PM5, PM14) These registers set input/output of ports 1, 3 to 5, 14 in 1-bit units. The presence or absence of timer I/O pins depends on the product. When using the timer array unit, set the following port mode registers according to the product used.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-25.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. (1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. (2) Any channel, except channel 0, can be set as a slave channel.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Example TAU0 CKm0 Channel 0: Master Channel group 1 (Simultaneous channel operation function) Channel 1: Slave Channel 2: Slave Channel group 2 (Simultaneous channel operation function) Channel 3: independent channel operation function CKm1 CKm0 Channel 4: Master * The operating clock of channel group 1 may be different from that of channel group 2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3, and there are several rules for using it. The basic rules for this function are as follows: (1) The 8-bit timer operation function applies only to channels 1 and 3.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (fTCLK) The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register mn (TMRmn). • Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits • Valid edge of input signal input from the TImn pin Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK) are shown below.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal input from the TImn pin is selected (CCSmn = 1) The count clock (fTCLK) is between fCLK to fCLK /215 by setting of timer clock select register m (TPSm). When a divided fCLK is selected, however, the count clock is not a signal which is simply divided fCLK by 2m, but a signal which becomes high level for one period of fCLK from its rising edge (m = 1 to 15).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-6. Table 6-6.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation. <2> A start trigger is generated at the first count clock after operation is enabled. <3> When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data register mn (TDRmn) is loaded to the TCRmn register to start counting.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation. <3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded to the TCRmn register and counting starts in the capture mode.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and count starts.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (5) Start timing in capture & one-count mode (operation at high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-33. Output Circuit Configuration <5> TOmn register Controller Interrupt signal of the master channel (INTTMmn) Interrupt signal of the slave channel (INTTMmp) Set TOmn pin Reset/toggle <1> <2> <3> <4> TOLmn TOMmn Internal bus TOEmn TOmn write signal The following describes the TOmn pin output circuit.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn Pin Output Setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-34.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.6.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output)) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting. Figure 6-36.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output level of the TOmn pin.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-38.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond to the relevant bits of the channel used to perform output (TOmn).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer (INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin. Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7) 6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.7 Timer Input (TImn) Control 6.7.1 TImn input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller. Enable the noise filter for the pin in need of noise removal. The following shows the configuration of the input circuit. Figure 6-43.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.8 Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Clock selection Figure 6-45. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 CKm0 Trigger selection Operation clockNote TSmn Timer counter register mn (TCRmn) Output controller Timer data register mn(TDRmn) Interrupt controller TOmn pin Interrupt signal (INTTMmn) Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Figure 6-46.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode) 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7) R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation TAU stop To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to be held is set to the port register. When holding the TOmn pin output level is not necessary Setting not required. The TAU0EN bit of the PER0 register is cleared to 0. Hardware Status The TOmn pin output level is held by port function.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt. The specified number of counts can be calculated by the following expression.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn 3 TCRmn 0000H TDRmn 2 3 1 2 0 1 2 0 0003H 1 2 0 1 0002H INTTMmn 4 events 4 events 3 events Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) 2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7) R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as frequency divider (channel 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin. The divided clock frequency output from TO00 can be calculated by the following expression.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Frequency Divider Function Is Used Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1. The pulse interval can be calculated by the following expression.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH b a TCRmn d c 0000H TDRmn 0000H a b c d INTTMmn OVF Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) 2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 0 12 11 CCSmn M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 1 1/0 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 1 0 1/0 Operation mode of channel n 010B: Capture mode Setting of operation when counting is started 0: Does not generate INTTMmn when counting is started.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control register (ISC) to 1. In the following descriptions, read TImn as RxD0. By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Operation clock Note CKm1 CKm0 Clock selection Figure 6-61. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement Timer counter register mn (TCRmn) TImn pin Noise filter Edge detection Trigger selection TNFEN1 Timer data register mn (TDRmn) Interrupt controller Interrupt signal (INTTMmn) Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Figure 6-62.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.8.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval. It can also generate INTTMmn (timer interrupt) at any interval by making a software set TSmn = 1 and the count down start during the period of TEmn = 1. The interrupt generation period can be calculated by the following expression.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn a b INTTMmn a+1 b+1 Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) 2. TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 1/0 12 11 CCSmn M/S 0 0 Note 0/1 10 9 8 7 6 5 4 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 1 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. 1: Trigger input is valid.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7) R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.9 Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin. The delay time and pulse width can be calculated by the following expressions.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master channel FFFFH TCRmn 0000H TDRmn a TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave channel 0000H TDRmp b TOmp INTTMmp a+2 b a+2 b Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p ≤ 7) 2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 0 12 CCSmn 0 0 11 10 9 8 7 6 5 4 MAS STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 TERmn 1 0 0 1 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) 15 TMRmp 14 13 CKSmp1 CKSmp0 1/0 0 12 11 CCSmp M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 1 0 0 0 3 2 1 0 MDmp3 MDmp2 MDmp1 MDmp0 0 1 0 0 0 Operation mode of channel p 100B: One-count mode Start trigger during operation 0: Trigger input is invalid.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable registers 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn and TSmp bits automatically return to 0 because they are trigger bits. Count operation of the master channel is started by start trigger detection of the master channel.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock CKm0 TSmn Trigger selection Master channel (interval timer mode) Clock selection Figure 6-74.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master channel TCRmn 0000H TDRmn a b TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave channel 0000H TDRmp c d TOmp INTTMmp a+1 c a+1 c b+1 d Remark 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p ≤ 7) 2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 0 11 10 9 8 7 6 5 4 0 0 MAS CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 TERmn CKSmn1 CKSmn0 1/0 12 0 0 1 0 0 0 0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 0 0 0 1 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 1: Generates INTTMmn when counting is started.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) 15 TMRmp 14 13 CKSmp1 CKSmp0 1/0 0 12 11 CCSmp M/S 0 Note 0 0 10 9 8 7 6 5 4 0 0 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 1 0 0 0 3 2 1 0 MDmp3 MDmp2 MDmp1 MDmp0 0 1 0 0 1 Operation mode of channel p 100B: One-count mode Start trigger during operation 1: Trigger input is valid.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Operation Procedure When PWM Function Is Used (2/2) Software Operation Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). Hardware Status The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. TEmn = 1, TEmp = 1 When the master channel starts counting, INTTMmn is The TSmn and TSmp bits automatically return to 0 generated.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock CKm0 TSmn Trigger selection Master channel (interval timer mode) Clock selection Figure 6-79.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-80. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) TSmn TEmn FFFFH Master channel TCRmn 0000H TDRmn a b TOmn INTTMmn TSmp TEmp FFFFH Slave channel 1 TCRmp 0000H TDRmp c d TOmp INTTMmp a+1 a+1 c c b+1 d d TSmq TEmq FFFFH Slave channel 2 TCRmq 0000H TDRmq e f TOmq INTTMmq a+1 e a+1 e b+1 f f (Remark is listed on the next page.) R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Remark 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q ≤ 7 (Where p and q are integers greater than n) 2.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-81.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-82.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.) start The TSmn bit (master), and TSmp and TSmq (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn, TSmp, and TSmq bits automatically return to 0 because they are trigger bits.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT 6.9.4 Remote control output function The PWM output function is applied to the remote control output function. The pairings of channels 2 and 3 and channels 6 and 7 are used to output the PWM signal (See 6.9.2 Operation as PWM function for how to set up each channel.). The PWM signal output from channel 3 is used as a mask wave, the PWM signal output from channel 7 is used as a carrier waves, and the logical products of these signals are output as remote control output.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-85. Procedure for Setting Remote Control Output (1/2) Software Operation Pin mode Sets the PFSEG17 bit of PFSEG2 register, PM32 bit of setting PM3 register, PU3 bit of PFSEG2 register and P32 bit of Hardware Status Remote control output is invaild P32/TO03 pin is low-level output P3 register to 1 Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-85. Procedure for Setting Remote Control Output (2/2) Software Operation Hardware Status Operation The cycle of the mask waveform (start code) and its highlevel width are set. start TDR02 = The cycle of the mask waveform - 1 TDR03 = High-level width of the mask waveform The cycle of the carrier waveform and its high-level width are set.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK CHAPTER 7 REAL-TIME CLOCK 7.1 Functions of Real-time Clock The real-time clock has the following features. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. • Constant-period interrupt function (period: 0.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Figure 7-1.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 3. R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 mode when the subsystem clock is used, by setting the RTCLPC bit of the subsystem clock supply mode control register (OSMC) to 1. In this case, set the RTCEN bit of the PER0 register to 1 and the other bits (bits 0 to 6) to 0. Be sure to clear the bits 1, 3, and 6 to 0.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the real-time clock operation clock (fRTC). In addition, by stopping clock functions that are an unnecessary, the RTCLPC bit can be used to reduce power consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.3 Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function. The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-4.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.4 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-5.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag 0 Constant-period interrupt is not generated. 1 Constant-period interrupt is generated. This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is generated, it is set to “1”. This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.5 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the counter (16-bit) overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later. Set a decimal value of 00 to 59 to this register in BCD code. The SEC register can be set by an 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.7 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Table 7-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 7-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 1) Time HOUR Register Time HOUR Register 0 00H 12 a.m. 12H 1 01H 1 a.m. 01H 2 02H 2 a.m. 02H 3 03H 3 a.m. 03H 4 04H 4 a.m. 04H 5 05H 5 a.m. 05H 6 06H 6 a.m. 06H 7 07H 7 a.m. 07H 8 08H 8 a.m. 08H 9 09H 9 a.m.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.8 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.9 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later. Set a decimal value of 00 to 06 to this register in BCD code. The WEEK register can be set by an 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.10 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later. Even if the day count register overflows while this register is being written, this register ignores the overflow and is set to the value written.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.12 Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16-bit) to the second count register (SEC) (reference value: 7FFFH). The SUBCUD register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-13.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 7-14.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm Day 12-Hour Display Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour Hour 24-Hour Display Hour Hour 10 1 Minute Minute 10 1 10 1 Minute Minute 10 1 W W W W W W W W W W W W W W 0 1 2 3 4 5 6 Every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 Every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 Every day, 11:59 a.m.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.4 Real-time Clock Operation 7.4.1 Starting operation of real-time clock Figure 7-19. Procedure for Starting Operation of Real-time Clock Start RTCEN = 1Note 1 RTCE = 0 Setting WUTMMCK0 Setting SEC Setting AMPM, CT2 to CT0 Supplies input clock. Stops counter operation. Sets fRTC Selects 12-/24-hour system and interrupt (INTRTC). Setting SEC Sets second count register. Setting MIN Sets minute count register. Setting HOUR Sets hour count register.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the first INTRTC interrupt has occurred. • Shifting to HALT/STOP mode when at least two input clocks (fRTC) have elapsed after setting the RTCE bit to 1 (see Figure 7-20, Example 1).
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 7-21. Procedure for Reading Real-time Clock Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Reading SEC Reads second count register. Reading MIN Reads minute count register. Reading HOUR Reads hour count register.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Figure 7-22. Procedure for Writing Real-time Clock Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Writing SEC Writes second count register. Writing MIN Writes minute count register. Writing HOUR Writes hour count register. Writing WEEK Writes week count register. Writing DAY Writing MONTH No Writes day count register. Writes month count register.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 7-23. Alarm processing Procedure Start WALE = 0 Match operation of alarm is invalid. WALIE = 1 Alarm match interrupts is valid. Setting ALARMWM Sets alarm minute register. Setting ALARMWH Sets alarm hour register. Setting ALARMWW Sets alarm week register. Match operation of alarm is valid.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.4.5 1 Hz output of real-time clock Figure 7-24. 1 Hz Output Setting Procedure Start RTCE = 0 Stops counter operation. Setting port Sets P31 and PM31 RCLOE1 = 1 Enables output of the RTC1HZ pin (1 Hz). RTCE = 1 Starts counter operation. Output start from RTC1HZ pin Cautions 1. First set the RTCEN bit to 1, while oscillation of the input clock (fSUB) is stable. 2. Pin output function of 1 Hz is not available in the 32-pin products. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK 7.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16-bit) is calculated by using the following expression. Set the DEV bit to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Correction example 1 Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz – 131.2 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 32.768 kHz from the PCLBUZ0 pin, or by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H). Note See 7.4.
R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 SEC 0000H Count start RSUBC count value 00 8054 8055 01 0000H 0001H 7FFFH + 56H (86) 7FFFH 19 0000H 0001H 7FFFH 0000H 20 8054H 8055H 39 0000H 0001H 7FFFH + 56H (86) 7FFFH 0000H 40 8054H 8055H 59 0000H 0001H 7FFFH + 56H (86) Figure 7-25.
RL78/L12 CHAPTER 7 REAL-TIME CLOCK Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H). Note See 7.4.5 1 Hz output of real-time clock for the setting procedure of outputting about 1 Hz from the RTC1HZ pin.
R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 SEC Register (16-bit) count value 0000H Count start 00 01 7FDAH 7FDBH 0000H 0001H 7FFFH-24H (36) 7FFFH 19 0000H 0001H 20 7FFFH 0000H 0001H 7FFFH 39 0000H 0001H 40 7FFFH 0000H 0001H 7FFFH 59 0000H 0001H Figure 7-26.
RL78/L12 CHAPTER 8 12-BIT INTERVAL TIMER CHAPTER 8 12-BIT INTERVAL TIMER 8.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter’s SNOOZE mode. 8.2 Configuration of 12-bit Interval Timer The 12-bit interval timer includes the following hardware. Table 8-1.
RL78/L12 CHAPTER 8 12-BIT INTERVAL TIMER 8.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the 12-bit interval timer is used, be sure to set bit 7 (RTCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 8 12-BIT INTERVAL TIMER 8.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the 12-bit interval timer operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 8 12-BIT INTERVAL TIMER 8.3.3 Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0FFFH. Figure 8-4.
RL78/L12 CHAPTER 8 12-BIT INTERVAL TIMER 8.4 12-bit Interval Timer Operation 8.4.1 12-bit interval timer operation timing The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate an 12-bit interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to 1, the 12-bit counter starts counting.
RL78/L12 CHAPTER 8 12-BIT INTERVAL TIMER 8.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock. Then, enter HALT or STOP mode.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER The number of output pins of the clock output and buzzer output controllers differs, depending on the product. Output pin 32-pin 44, 48, 52, 64-pin PCLBUZ0 √ √ PCLBUZ1 − √ Caution Most of the following descriptions in this chapter use the 64-pin as an example. 9.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-1.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 9-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers Configuration Peripheral enable register 0 (PER0) Clock output select registers n (CKSn) Port mode registers 5, 14 (PM5, PM14) Port registers 5, 14 (P5, P14) 9.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the clock output/buzzer output controller is used in subsystem clock (fSUB), be sure to set bit 7 (RTCEN) of this register to 1.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.3.2 Clock output select registers n (CKSn) These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and set the output clock. Select the clock to be output from the PCLBUZn pin by using the CKSn register. The CKSn register are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 9-3.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Notes 1. Use the output clock within a range of 16 MHz. Furthermore, when using the output clock at 2.7 V ≤ VDD < 4.0 V, can be use it within 8 MHz only. See 30.4 or 31.4 AC Characteristics for details. 2. Do not select fSUB as the clock output from the clock output/buzzer output controller when the WUTMMCK0 bit of the OSMC register is set to 1. Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0). 2.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.3.3 Port mode registers 5, 14 (PM5, PM14) These registers set input/output of port 5, 14 in 1-bit units. When using the P50/INTP5/SEG7/(PCLBUZ0), P140/PCLBUZ0/TO00/SEG27 and P141/PCLBUZ1/TI00/SEG26 pins for clock output and buzzer output, clear PM50, PM140 and PM141 bits and the output latches of P50, P140 and P141 to 0. The PM5 and PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1). 9.4.1 Operation as output pin The PCLBUZn pin is output as the following procedure.
RL78/L12 CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (fIL). The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
RL78/L12 CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte. Table 10-2.
RL78/L12 CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 10-2.
RL78/L12 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 25).
RL78/L12 CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT, STOP, and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 In HALT mode WDSTBYON = 1 Watchdog timer operation stops. Watchdog timer operation continues. In STOP mode In SNOOZE mode If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is cleared to 0 and counting starts.
RL78/L12 CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. • If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer is cleared and starts counting again.
RL78/L12 CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 29/fIL, the window close time and open time are as follows. Setting of Window Open Period 50% 75% 100% Window close time 0 to 20.08 ms 0 to 10.04 ms None Window open time 20.08 to 29.68 ms 10.04 to 29.68 ms 0 to 29.68 ms • Overflow time: 29/fIL (MAX.) = 29/17.25 kHz = 29.68 ms • Window close time: 0 to 29/fIL (MIN.) × (1 − 0.5) = 0 to 29/12.75 kHz × 0.5 = 0 to 20.
RL78/L12 CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product. 32-pin 44-pin 48-pin 52, 64-pin Analog 4 ch 7 ch 9 ch 10 ch input (ANI0, ANI1, (ANI0, ANI1, (ANI0, ANI1, (ANI0, ANI1, channels ANI18, ANI19) ANI17 to ANI21) ANI16 to ANI22) ANI16 to ANI23) Caution Most of the following descriptions in this chapter use the 64-pin as an example. 11.
PMCxx Temperature sensor ADS4 ADS3 ADS1 ADS0 A/D converter mode register 2 (ADM2) 5 Controller A/D converter mode register 1 (ADM1) FR2 Internal bus ADCS Successive approximation register (SAR) ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 ADTYP 3 VSS FR1 FR0 5 LV1 LV0 Comparison voltage generator ADCE ADREFM bit A/D conversion result upper limit/lower limit comparator INTAD Timer trigger signal (INTRTC) Timer trigger signal (INTIT) Timer trigger signal (INTTM01) A/D conversion result registe
RL78/L12 CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0, ANI1 and ANI16 to ANI23 pins These are the analog input pins of the 10 channels of the A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
RL78/L12 CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter uses the following registers.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-3.
RL78/L12 CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation 0 0 Stop status 0 1 Conversion standby mode 1 0 Setting prohibited 1 1 Conversion mode Table 11-2.
RL78/L12 CHAPTER 11 A/D CONVERTER Figure 11-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Software trigger mode Conversion standby ADCS Conversion standby ADCS Trigger standby 0 is written to ADCS. Conversion start Note 2 Conversion Conversion operation standby Conversion stopped Note 1 Hardware trigger detection 0 is written 1 is written to ADCS. Conversion start Note 2 to ADCS.
RL78/L12 CHAPTER 11 A/D CONVERTER Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby status. 2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained.
RL78/L12 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (1/4) (1) When there is no stabilization wait time Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 FR1 FR0 Conversion Number of Conversion Clock (fAD) Conversion (ADM0) FR2 Mode LV1 Cycles 0 0 0 0 0 Normal 1 fCLK/64 Note 3 19 fAD 1216/fCLK (number 0 0 1 2.7 V ≤ VDD ≤ 5.
RL78/L12 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (2/4) (2) When there is no stabilization wait time Note 1 Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 FR2 0 FR1 FR0 0 0 Mode Conversion Number of Conversion Clock (fAD) Conversion (ADM0) LV1 1 LV0 0 Low- fCLK/64 voltage 1 Conversion Time Selection 1.6 V ≤ VDD ≤ 5.
RL78/L12 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (3/4) (3) When there is stabilization wait time Normal mode 1, 2 (hardware trigger wait mode A/D Converter Mode Register 0 FR1 FR0 ) Mode Conversion Number of Number of Stabilization Conversion Time Selection 2.7 V ≤ VDD ≤ 5.
RL78/L12 CHAPTER 11 A/D CONVERTER Table 11-3.
RL78/L12 3. CHAPTER 11 A/D CONVERTER The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. 4. When hardware trigger wait mode, specify the conversion time, including the stabilization wait time from the hardware trigger detection. Remark fCLK: CPU/peripheral hardware clock frequency Figure 11-5.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-6.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.4 A/D converter mode register 2 (ADM2) This register is used to select the + side or - side reference voltage of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-7.
RL78/L12 CHAPTER 11 A/D CONVERTER Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H R/W Symbol 7 6 5 4 <3> <2> 1 <0> ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP AWC Specification of the SNOOZE mode 0 Do not use the SNOOZE mode function. 1 Use the SNOOZE mode function.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.5 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH Note .
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored Note . The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-11.
RL78/L12 CHAPTER 11 A/D CONVERTER Cautions 9. Do not set the ADISS bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is operating on the subsystem clock. Also, if the ADREFP1 bit is set to 1, the A/D converter reference voltage current (IADREF) indicated in 30.3.2 Supply current characteristics or 31.3.2 Supply current characteristics will be added to the current consumption when shifting to HALT mode while the CPU is operating on the main system clock. 11.3.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or - side reference voltage for the converter, an analog input channel (ANIxx), the temperature sensor output voltage, or the internal reference voltage (1.45 V) as the target for A/D conversion. When using this register to test the converter, set as follows. • For zero-scale measurement, select the - side reference voltage as the target for conversion.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <3> Bit 9 of the successive approximation register (SAR) is set.
RL78/L12 CHAPTER 11 A/D CONVERTER Figure 11-15. Conversion Operation of A/D Converter (Software Trigger Mode) 1 is written to ADCS ADCS Conversion time Conversion start time A/D converter Conversion Conversion standby start operation SAR Sampling time Sampling A/D conversion Undefined ADCR Conversion standby Conversion result Conversion result INTAD In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0, ANI1, ANI16 to ANI23) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF × 1024 + 0.5) ADCR = SAR × 64 or ( ADCR 64 − 0.5) × where, INT( ): AVREF 1024 ≤ VAIN < ( ADCR 64 + 0.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 11.7 A/D Converter Setup Flowchart. 11.6.1 Software trigger mode (sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.6.2 Software trigger mode (one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1.0 μ s), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
RL78/L12 CHAPTER 11 A/D CONVERTER 11.6.3 Hardware trigger no-wait mode (sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1.0 μ s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage).
RL78/L12 CHAPTER 11 A/D CONVERTER 11.6.4 Hardware trigger no-wait mode (one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1.0 μ s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage).
RL78/L12 CHAPTER 11 A/D CONVERTER 11.6.5 Hardware trigger wait mode (sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS).
RL78/L12 CHAPTER 11 A/D CONVERTER 11.6.6 Hardware trigger wait mode (one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS).
RL78/L12 CHAPTER 11 A/D CONVERTER 11.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. 11.7.1 Setting up software trigger mode Figure 11-23. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.7.2 Setting up hardware trigger no-wait mode Figure 11-24. Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMCx register settings ANI0 and ANI1 pins: Set using the ADPC register ANI16 to ANI23 pins: Set using the PMCx register PM register setting The ports are set to the input mode.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.7.3 Setting up hardware trigger wait mode Figure 11-25. Setting up Hardware Trigger Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMCx register settings ANI0 and ANI1 pins: Set using the ADPC register ANI16 to ANI23 pins: Set using the PMCx register PM register setting The ports are set to the input mode.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.7.4 Setup when temperature sensor output/internal reference voltage output is selected (example for software trigger mode and one-shot conversion mode) Figure 11-26. Setup when temperature sensor output/internal reference voltage output is selected Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. • ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.7.5 Setting up test mode Figure 11-27. Setting up Test Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. • ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. • ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: This is used to specify the one-shot conversion mode.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger. This is effective for reducing the operation current.
RL78/L12 CHAPTER 11 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
RL78/L12 CHAPTER 11 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
RL78/L12 CHAPTER 11 A/D CONVERTER (3) Operation when A/D conversion is interrupted or resumed If A/D conversion is interrupted (by clearing bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0), the clock request signal (an internal signal) is set to the low level, and supplying the high-speed on-chip oscillator clock stops.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits.
RL78/L12 CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
RL78/L12 CHAPTER 11 A/D CONVERTER 11.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start operation.
RL78/L12 CHAPTER 11 A/D CONVERTER Figure 11-38. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREFP and VDD or equal to or lower than AVREFM and VSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREFP or VDD ANI0, ANI1 and ANI16 to ANI23 C = 100 to 1,000 pF (5) Analog input (ANIn) pins <1> The analog input pins (ANI0 and ANI1) are also used as input port pins (P20 and P21).
RL78/L12 CHAPTER 11 A/D CONVERTER Figure 11-39. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ANIn ADCR ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF (8) Conversion results just after A/D conversion start In software trigger mode and hardware trigger no-wait mode, if the ADCE bit is set to 1 and then the ADCS bit is set to 1 before 1.
RL78/L12 CHAPTER 11 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-40. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREFP, VDD ANIn Pins R1 [kΩ] C1 [pF] C2 [pF] 3.6 V ≤ VDD ≤ 5.5 V ANI0 and ANI1 14 8 2.5 ANI16 to ANI23 18 8 7.0 ANI0 and ANI1 39 8 2.5 ANI16 to ANI23 53 8 7.0 ANI0 and ANI1 231 8 2.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT CHAPTER 12 SERIAL ARRAY UNIT Serial array unit has two serial channels. Each channel can achieve 3-wire serial (CSI), and UART. Function assignment of each channel supported by the RL78/L12 is as shown below. Channel Used as CSI Used as UART 0 CSI00 UART0 (supporting LIN-bus) 1 CSI01 12.1 Functions of Serial Array Unit Each serial interface supported by the RL78/L12 has the following features. 12.1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0) This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 12-1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of the serial array unit. Figure 12-1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin. The shift register cannot be directly manipulated by program.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2. Format of Serial Data Register mn (SDRmn) (mn = 00, 01) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF11H (SDR00) 15 14 13 12 11 R/W FFF10H (SDR00) 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 SDRmn Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 12.3 Registers Controlling Serial Array Unit. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit is used, be sure to set bit 2 (SAU0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the PER0 register to 00H.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits 3 to 0. Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1). The SPSm register can be set by a 16-bit memory manipulation instruction.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI, or UART), and an interrupt source. This register is also used to invert the level of the receive data only in the UART mode.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-5. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00), F0112H, F0113H (SMR01) Symbol 15 14 13 12 11 10 9 SMRmn CKS CCS 0 0 0 0 0 mn mn After reset: 0020H 8 7 STS 0 mn Note R/W 6 5 4 3 2 SIS 1 0 0 0 mn0 1 0 MD MD mn1 mn0 Note SIS Controls inversion of level of receive data of channel n in UART mode mn0 0 Falling edge is detected as the start bit.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00), F011AH, F011BH (SCR01) After reset: 0087H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 SLC SLC 0 1 DLS DLS mn mn mn mn mn mn1 mn0 mn mn1 mn0 mn1 mn0 Note 1 TXE RXE mn mn 0 0 Disable communication.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that sets the division ratio of the operation clock (fMCK).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared immediately when the corresponding bit of the SSRmn register is cleared.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-9. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01) After reset: 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SSRmn 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 mn mn FEF mn 2 1 0 FEF PEF OVF mn mn Note mn Framing error detection flag of channel n Note 0 No error occurs. 1 An error occurs (during UART reception).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1. The SSm register can be set by a 16-bit memory manipulation instruction.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n. The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode. Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn = 1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.14 Serial standby control register m (SSCm) The SSCm register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSCm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSCm register can be set with an 8-bit memory manipulation instruction with SSCmL. Reset signal generation clears the SSCm register to 0000H.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-18. Interrupt in UART Reception Operation in SNOOZE Mode EOCmn Bit SSECm Bit Reception Ended Successfully Reception Ended in an Error 0 0 INTSRx is generated. INTSRx is generated. 0 1 INTSRx is generated. INTSRx is generated. 1 0 INTSRx is generated. INTSREx is generated. 1 1 INTSRx is generated. No interrupt is generated. 12.3.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. Disable the noise filter of the pin used for CSI communication, by clearing the corresponding bit of this register to 0. Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.3.17 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx), port mode control register (PMCxx)). For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), 4.3.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation stop mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode. 12.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 12-22. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable stopping communication/count by each channel.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01) are channels 0 and 1. Channel Used as CSI Used as UART 0 CSI00 UART0 (supporting LIN-bus) 1 CSI01 3-wire serial I/O (CSI00, CSI01) performs the following seven types of communication operations. • Master transmission (See 12.5.1.) • Master reception (See 12.5.2.) • Master transmission/reception (See 12.5.3.) • Slave transmission (See 12.5.4.) • Slave reception (See 12.5.5.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-23.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-23. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 1 0 SOEm1 SOEm0 0/1 0/1 1 0 SSm1 SSm0 0/1 0/1 (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-24. Initial Setting Procedure for Master Transmission Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-25. Procedure for Stopping Master Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target No (Essential) Slave ready? (slave) or communication operation completed Yes Disable data output and clock output of Port manipulation (Essential) the target channel by setting a port register and a port mode register.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-27.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-28. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 12-24. (Select Transfer end interrupt) Main routine Set data for transmission and the number of data.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-29.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-30. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting For the initial setting, refer to Figure 12-24. (Select buffer empty interrupt) Set data for transmission and the number of data.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master reception Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 Channel 1 Pins used SCK00, SI00 SCK01, SI01 Interrupt INTCSI00 INTCSI01 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-31.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-31. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 1 0 SOEm1 SOEm0 × × 1 0 SSm1 SSm0 0/1 0/1 (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-32. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target Completing slave preparations? (Essential) No Yes Port manipulation (Essential) (slave) or communication operation completed Disable clock output of the target channel by setting a port register and a port mode register. (Selective) Re-set the register to change the operation Changing setting of the SPSm register clock setting.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-35.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-36. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Setting receive data Enables interrupt Writing dummy data to SIOp (=SDRmn[7:0]) For the initial setting, refer to Figure 12-32.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 12-37.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-38. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 12-32.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master transmission/reception Master transmission/reception is that the RL78/L12 outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 Channel 1 Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 Interrupt INTCSI00 INTCSI01 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-39.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-39. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 1 0 SOEm1 SOEm0 0/1 0/1 1 0 SSm1 SSm0 0/1 0/1 (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-40. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-41. Procedure for Stopping Master Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-42. Procedure for Resuming Master Transmission/Reception Starting setting for resumption (Essential) Completing slave preparations? No Yes (Selective) Port manipulation Wait until stop the communication target (slave) or communication operation completed Disable data output and clock output of the target channel by setting a port register and a port mode register.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-43.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-44. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 12-40.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-45.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-46. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting For the initial setting, refer to Figure 12-40.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave transmission Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 Channel 1 Pins used SCK00, SO00 SCK01, SO01 Interrupt INTCSI00 INTCSI01 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-47.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-47. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 1 0 SOEm1 SOEm0 0/1 0/1 1 0 SSm1 SSm0 0/1 0/1 (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-48. Initial Setting Procedure for Slave Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Setting the SDRmn register Set bits 15 to 9 to 0000000B for baud rate setting.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-49. Procedure for Stopping Slave Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Procedure for Resuming Slave Transmission Starting setting for resumption Completing master preparations? (Essential) No Yes Port manipulation (Selective) Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-51.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-52. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 12-48.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-53.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-54. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting Main routine Setting transmit data For the initial setting, refer to Figure 12-48.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave reception Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 Channel 1 Pins used SCK00, SI00 SCK01, SI01 Interrupt INTCSI00 INTCSI01 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-55.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-55. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) …The Register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 1 0 SOEm1 SOEm0 × × 1 0 SSm1 SSm0 0/1 0/1 (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-56. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set baud rate setting (bits 15 to 9) to Setting the SDRmn register 0000000B.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-58.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-59.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-60. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Ready for reception For the initial setting, refer to Figure 12-56.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave transmission/reception Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-61.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 1 0 SOEm1 SOEm0 0/1 0/1 1 0 SSm1 SSm0 0/1 0/1 (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-62. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-63. Procedure for Stopping Slave Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Completing master preparations? (Essential) No Yes (Essential) Port manipulation Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-65.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-66.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-67.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-68.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 SNOOZE mode function SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input. Only the following channel can be set to the SNOOZE mode.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) SNOOZE mode operation (once startup) Figure 12-69.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-70.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 12-71.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-72.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz] (2) Slave (Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}Note [Hz] Note The permissible maximum transfer clock frequency is fMCK/6.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Table 12-2. Selection of Operation Clock For 3-Wire Serial I/O SMRmn Register SPSm Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 1 Note fCLK = 24 MHz X X X X 0 0 0 0 fCLK X X X X 0 0 0 1 fCLK/2 24 MHz 12 MHz X X X X 0 0 1 0 fCLK/2 2 X X X X 0 0 1 1 fCLK/2 3 3 MHz 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01) communication is described in Figure 12-73. Figure 12-73. Processing Procedure in Case of Overrun Error Software Manipulation Reads serial data register mn (SDRmn).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0) Communication This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT UART0 uses channels 0 and 1. Channel Used as CSI Used as UART 0 CSI00 UART0 (supporting LIN- 1 CSI01 bus) Caution When using serial array unit as UARTs, the channels of both the transmitting side (even-number channel) and the receiving side (odd-number channel) can be used only as UARTs. UART performs the following four types of communication operations. • UART transmission (See 12.6.1.) • UART reception (See 12.6.2.) • LIN transmission (See 12.7.1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART transmission UART transmission is an operation to transmit data from the RL78/L12 to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission. UART UART0 Target channel Channel 0 Pins used TxD0 Interrupt INTST0 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-74.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-74. Example of Contents of Registers for UART Transmission of UART (UART0) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel. 15 14 13 12 11 10 0 0 0 0 0 0 SOm 9 8 7 6 5 4 3 2 0 0 0 0 0 0 CKOm1 CKOm0 × × 1 0 SOm1 SOm0 × 0/1Not e 0: Serial data output value is “0” 1: Serial data output value is “1” (f) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-75. Initial Setting Procedure for UART Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-76. Procedure for Stopping UART Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-77. Procedure for Resuming UART Transmission Starting setting for resumption Completing master preparations? (Essential) Yes (Selective) Port manipulation No Wait until stop the communication target or communication operation completed Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the (Selective) Changing setting of the SPSm register operation clock setting.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-78.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-79. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication SAU default setting For the initial setting, refer to Figure 12-75. (Select transfer end interrupt) Main routine Set data for transmission and the number of data.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-80.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-81. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication <1> SAU default setting For the initial setting, refer to Figure 12-75. (Select buffer empty interrupt) Set data for transmission and the number of data.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART reception UART reception is an operation wherein the RL78/L12 asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set. UART UART0 Target channel Channel 1 Pins used RxD0 Interrupt INTSR0 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-82.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-82. Example of Contents of Registers for UART Reception of UART (UART0) (2/2) (e) Serial output register m (SOm) … The register that not used in this mode. 15 14 13 12 11 10 0 0 0 0 0 0 SOm 9 8 7 6 5 4 3 2 0 0 0 0 0 0 CKOm1 CKOm0 × × 1 0 SOm1 SOm0 × × 1 0 (f) Serial output enable register m (SOEm) …The register that not used in this mode.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-83. Initial Setting Procedure for UART Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Set an operation mode, etc. Setting the SMRmn and SMRmr registers Set a communication format.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-85. Procedure for Resuming UART Reception Starting setting for resumption Completing master preparations? (Essential) No Stop the target for communication or wait until completes its communication operation. Yes (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-86.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-87. Flowchart of UART Reception Starting UART communication SAU default setting Main routine Setting receive data Enables interrupt For the initial setting, refer to Figure 12-83.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation upon detection of the RxDq pin input. Only the following channel can be set to the SNOOZE mode.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. Baud Rate Setting for UART Reception in SNOOZE Mode Baud Rate for UART Reception in SNOOZE Mode High-speed On-chip Oscillator (fIH) Baud Rate of 4800 bps Maximum Minimum Permissible SDRmn[15:9] Permissible Value Value fCLK/2 5 105 2.27% −1.53% fCLK/2 5 79 1.60% −2.18% fCLK/2 4 105 2.27% −1.53% Operation Clock (fMCK) 32 MHz ± 1.0% Note 24 MHz ± 1.0% Note 16 MHz ± 1.0% Note 12 MHz ± 1.0% Note fCLK/2 4 79 1.60% −2.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSREq) is not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSRq) will be generated. Figure 12-88.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled) Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs. Figure 12-89.
RL78/L12 Figure 12-90. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) Setting start No Does TSFmn = 0 on all channels? Yes Normal operation <1> Writing 1 to the STmn bit → SEmn = 0 SAU default setting STOP mode. Channel 1 is specified for UART reception. (EOCmn: Enable error interrupt.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Remarks 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 12-88 Timing Chart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 12-89 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0). 2. m = 0; q = 0 (3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped) Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs. Figure 12-91.
RL78/L12 Figure 12-92. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1) Setting start Does TSFmn = 0 on all channels? No Yes Normal operation SIRm1 = 0007H <1> Writing 1 to the STmn bit → SEmn = 0 SAU default setting Channel 1 is specified for UART reception. (EOCmn: Enable error interrupt.) SNOOZE mode setting (make the setting to enable generation of error interrupt INTSREq in SNOOZE mode).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9 bits). Remarks 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited. Remarks 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Table 12-4. Selection of Operation Clock For UART SMRmn Register SPSm Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 1 Operation Clock (fMCK) Note fCLK = 24 MHz X X X X 0 0 0 0 fCLK X X X X 0 0 0 1 fCLK/2 24 MHz 12 MHz X X X X 0 0 1 0 fCLK/2 2 X X X X 0 0 1 1 fCLK/2 3 3 MHz 1.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. (Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 − 100 [%] Here is an example of setting a UART baud rate at fCLK = 24 MHz.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Procedure for processing errors that occurred during UART (UART0) communication The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 12-94 and 12-95. Figure 12-94. Processing Procedure in Case of Parity Error or Overrun Error Software Manipulation Hardware Status Remark Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the (SDRmn).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.7 LIN Communication Operation 12.7.1 LIN transmission UART0 transmission supports LIN communication. For LIN transmission, channel 0 is used. UART UART0 Support of LIN communication Supported Target channel Channel 0 Pins used TxD0 Interrupt INTST0 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag None Transfer data length 8 bits Transfer rate Max.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. Communication of LIN is single-master communication and up to 15 slaves can be connected to one master. The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN. Usually, the master is connected to a network such as CAN (Controller Area Network).
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-97.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 LIN reception UART0 reception supports LIN communication. For LIN reception, channel 1 is used. UART UART0 Support of LIN communication Supported Target channel Channel 1 Pins used RxD0 Interrupt INTSR0 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-98.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-99. Flowchart for LIN Reception Status of LIN bus signal and operation of the hardware Starting LIN communication Generate INTP0? No Wakeup signal frame Wait for wakeup frame Note signal RxD0 pin Edge detection Yes The low-level width of RxD0 is measured using TM05 and BF is detected.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-100 and figure 12-101 show the configuration of a port that manipulates reception of LIN. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0). The length of the sync field transmitted from the master can be measured by using the external event capture operation of the timer array unit to calculate a baud-rate error.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-101.
RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT The peripheral functions used for the LIN communication operation are as follows. • External interrupt (INTP0); Wakeup signal detection Usage: To detect an edge of the wakeup signal and the start of communication • Channel 5 of timer array unit; Baud rate error detection, break field detection.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA CHAPTER 13 SERIAL INTERFACE IICA 13.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLA0) line and a serial data bus (SDAA0) line.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-1.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 SDAA0 Slave CPU1 Address 0 SCLA0 Serial data bus Serial clock SDAA0 Slave CPU2 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 13-1.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (2) Slave address register 0 (SVA0) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVA0 register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected). Reset signal generation clears the SVA0 register to 00H. Figure 13-4.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (11) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1. (12) Stop condition generator This circuit generates a stop condition when the SPT0 bit is set to 1.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. • Peripheral enable register 0 (PER0) • IICA control register 00 (IICCTL00) • IICA flag register 0 (IICF0) • IICA status register 0 (IICS0) • IICA control register 01 (IICCTL01) • IICA low-level width setting register 0 (IICWL0) • IICA high-level width setting register 0 (IICWH0) • Port mode register 6 (PM6) • Port register 6 (P6) 13.3.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.3.2 IICA control register 00 (IICCTL00) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is set from “0” to “1”. Reset signal generation clears this register to 00H.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (1/4) Address: F0230H (IICCTL00) After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable Note 1 0 Stop operation. Reset the IICA status register 0 (IICS0) 1 Enable operation. . Stop internal operation. Be sure to set this bit (1) while the SCLA0 and SDAA0 lines are at high level.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable If the WUP0 bit of IICA control register 01 (IICCTL01) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4) STT0 Start condition trigger Notes 1, 2 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: • When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (4/4) SPT0 Note Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing • For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and slave has been notified of final reception.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.3.3 IICA status register 0 (IICS0) This register indicates the status of I2C. The IICS0 register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H. Caution Reading the IICS0 register while the address match wakeup function is enabled (WUP0 = 1) in STOP mode is prohibited.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension code reception 0 Extension code was not received. 1 Extension code was received.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-8.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.3.5 IICA control register 01 (IICCTL01) This register is used to set the operation mode of I2C and detect the statuses of the SCLA0 and SDAA0 pins. The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only. Set the IICCTL01 register, except the WUP0 bit, while operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0).
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) 0 The SCLA0 pin was detected at low level. 1 The SCLA0 pin was detected at high level.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.3.6 IICA low-level width setting register 0 (IICWL0) This register is used to set the low-level width (tLOW) and data hold time (tHD:DAT) of the SCLA0 pin signal that is output by serial interface IICA. The data hold time is decided by value the higher 6 bits of IICWL register. The IICWL0 register can be set by an 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.3.8 Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0/SEG21 pin as clock I/O and the P61/SDAA0/SEG20 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set the IICE0 bit (bit 7 of IICA control register 00 (IICCTL00)) to 1 before setting the output mode because the P60/SCLA0/SEG21 and P61/SDAA0/SEG20 pins output a low level (fixed) when the IICE0 bit is 0.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.4 I2C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 .... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAA0 .... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock on master side fCLK Transfer clock = IICWL0 + IICWH0 + fCLK (tR + tF) At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows. (The fractional parts of all setting values are rounded up.) • When the fast mode 0.52 × fCLK Transfer clock 0.48 − tR − tF) × fCLK IICWH0 = ( Transfer clock IICWL0 = • When the normal mode 0.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK operation frequency for serial interface IICA is determined according to the mode. Fast mode: fCLK = 3.5 MHz (MIN.) Fast mode plus: fCLK = 10 MHz (MIN.) Normal mode: fCLK = 1 MHz (MIN.) In addition, the fastest operation frequency of the operation clock of the serial interface IICA is 20 MHz (Max.).
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus. Figure 13-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C bus’s serial data bus. Figure 13-14.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 13-19.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 13-20.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-20.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.7 Canceling wait The I2C usually cancels a wait state by the following processing.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 13-2. Table 13-2.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when the address set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been received. 13.5.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Table 13-4.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-23. Flow When Setting WUP0 = 0 upon Address Match (Including Extension Code Reception) STOP mode state No INTIICA0 = 1? Yes WUP0 = 0 Wait Waits for 5 clocks. Reading IICS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICA0 START SPIE0 = 1 WUP0 = 1 STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0. WUP0 = 0 No INTIICA0 = 1? Yes Wait Generates a STOP condition or selects as a slave device. Waits for 5 clocks.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-25 shows the communication reservation timing. Figure 13-25.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-27. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note 2 Yes MSTS0 = 0? Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait timeNote 1 by software.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 1) When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.15 Cautions (1) When STCEN = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the RL78/L12 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 13-28. Master Operation in Single-Master System START Initializing I2C busNote Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3.8 Port mode register 6 (PM6)). Initial setting Setting port IICWL0, IICWH0 ← XXH Sets a transfer clock. SVA0 ← XXH Sets a local address.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 13-29. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3.8 Port mode register 6 (PM6)). Setting port IICWL0, IICWH0 ← XXH Selects a transfer clock. SVA0 ← XXH Sets a local address. IICF0 ← 0XH Setting STCEN0 and IICRSV0 Sets a start condition.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STT0 = 1 Secure wait timeNote by software. Wait Communication processing Prepares for starting communication (generates a start condition). MSTS0 = 1? No Yes INTIICA0 interrupt occurs? No Waits for bus release (communication being reserved).
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (3/3) C Writing IICA0 INTIICA0 interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTS0 = 1? No Yes No 2 ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Communication processing WTIM0 = 1 WREL0 = 1 Writing IICA0 Starts transmission. INTIICA0 interrupt occurs? INTIICA0 interrupt occurs? No Waits for data transmission.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B 3: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 4: IICS0 = 1000××00B (Sets the SPT0 bit to 1)Note 5: IICS0 = 00000001B Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 1 3: IICS0 = 1000××00B (Clears the WTIM0 bit to 0Note 2, sets the STT0 bit to 1) 4: IICS0 = 1000×110B 5: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 3 6: IICS0 = 1000××00B (Sets th
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B 3: IICS0 = 1010×000B (Sets the WTIM0 bit to 1)Note 4: IICS0 = 1010××00B (Sets the SPT0 bit to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0 interrupt request signal.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001×110B 2: IICS0 = 0
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×110B 4: IICS0 = 0001×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0010×010B 4: IICS0 = 0010×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match addres
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 00000×10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not extensio
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0001×110B 4: IICS0 = 0001×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0010×010B 4: IICS0 = 0010×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 00000×10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0110×010B 2: IICS0 = 0010×000B 3: IICS0 = 0010×000
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request si
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICS0 = 1000×110B 2: IICS0 = 01000110B 3: IICS0
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICS0 = 10000110B 2: IICS0 = 01000001B Remark : Always generated : Gener
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000×100B (Clears the WTIM0 bit to 0) 4: IICS0 = 01000000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000××00B (Sets the STT0 bit to 1) 4: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 AC
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000×100B (Clears the WTIM0 bit to 0) 4: IICS0 = 01000100B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 =
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA 13.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 13-32 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 = 1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start condition is subsequently detected, the master device enters the master device communication status (MSTS0 = 1).
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 13-32 are explained below. <3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 13-32 are explained below. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The following describes the operations in Figure 13-32 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <1> to <3> are performed. These steps return the processing to step <3>, the data transmission step. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 13-33 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start condition is subsequently detected, the master device enters the master device communication status (MSTS0 = 1).
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 13-33 are explained below. <3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33.
RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 13-33 are explained below. <8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICA0: end of transfer). Because of ACKE0 = 0 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the wait status (WREL0 = 1).
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER CHAPTER 14 LCD CONTROLLER/DRIVER The number of LCD display function pins of the RL78/L12 differs depending on the product. The following table shows the number of pins of each product. Table 14-1. Number of LCD Display Function Pins of Each Product (1/3) (a) 32-pin and 44-pin products Part No.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-1. Number of LCD Display Function Pins of Each Product (2/3) (b) 48-pin and 52-pin products Part No.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-1. Number of LCD Display Function Pins of Each Product (3/3) (c) 64-pin products Part No.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-2 lists the maximum number of pixels that can be displayed in each display mode. Table 14-2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-2.
R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 2 VLCON CAPH CAPL VL1 VL2 VL4 2 LCD mode register 1 (LCDM1) LCDON SCOC VLCON BLON LCDSEL LCDVLM VL3 6 LCD boost level control register (VLCD) Common voltage controller Segment voltage controller Internal bus COM0 INTRTC . . . . . . . . COM3 COM4/ SEG0 . . . . . . . . COM7/ SEG3 Segment driver 76543210 Selector 00H 76543210 INTLCD0 LCDON Common driver Timing controller 5 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 Internal bus ........... ...........
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3 Registers Controlling LCD Controller/Driver The following ten registers are used to control the LCD controller/driver.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.1 Peripheral enable register 0 (PER0) PER0 enables or disables supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the LCD controller/driver is used in subsystem clock (fSUB), be sure to set bit 7 (RTCEN) of this register to 1. This register is set by using a 1-bit or 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.2 LCD mode register 0 (LCDM0) LCDM0 specifies the LCD operation. This register is set by using an 8-bit memory manipulation instruction. Reset signal generation sets LCDM0 to 00H. Figure 14-3.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-3. Format of LCD Mode Register 0 (LCDM0) (2/2) Address: FFF40H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 LCDM0 MDSET1 MDSET0 LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0 LBAS1 LBAS0 0 0 1/2 bias method 0 1 1/3 bias method 1 0 1/4 bias method 1 1 Setting prohibited LCD display bias mode selection Cautions 1. Do not rewrite the LCDM0 value while the SCOC bit of the LCDM1 register = 1. 2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.3 LCD mode register 1 (LCDM1) LCDM1 enables or disables display operation, voltage boost circuit operation, and capacitor split circuit operation, and specifies the display data area and the low voltage mode. LCDM1 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LCDM1 to 00H. Figure 14-4.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-4. Format of LCD Mode Register 1 (LCDM1) (2/2) After reset: 00H Address: FFF41H R/W Symbol <7> <6> <5> <4> <3> 2 1 <0> LCDM1 LCDON SCOC VLCON BLON LCDSEL 0 0 LCDVLM LCDVLM Note Control of default value of voltage boosting pin 0 Set when VDD ≥ 2.7 V 1 Set when VDD ≤ 4.2 V Note This bit is used to boost the voltage efficiently when using the voltage boost circuit by setting the initial VLX pin status. If VDD is 2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.4 Subsystem clock supply mode control register (OSMC) OSMC is used to reduce power consumption by stopping as many unnecessary clock functions as possible. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock, 12-bit interval timer, clock output/buzzer output, and LCD controller/driver, is stopped in HALT mode while the subsystem clock is selected as the CPU clock.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.5 LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and the number of time slices. This register is set by using an 8-bit memory manipulation instruction. Reset signal generation sets LCDC0 to 00H. Figure 14-6.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-6.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.6 LCD boost level control register (VLCD) VLCD selects the reference voltage that is to be generated when operating the voltage boost circuit (contrast adjustment). The reference voltage can be selected from 16 steps. This register is set by using an 8-bit memory manipulation instruction. Reset signal generation sets VLCD to 04H. Figure 14-7.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.7 LCD input switch control register (ISCLCD) Input to the schmitt trigger buffer must be invalid until the CAPL/P126, CAPH/P127, and VL3/P125 pins are set to operate as LCD function pins in order to prevent through-current from entering. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets ISCLCD to 00H. Figure 14-8.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER The following shows the VL3/P125 pin function status transitions. Figure 14-9. VL3/P125 Pin Function Status Transitions Reset status LBAS1, LBAS0 = 10 Reset release Digital input ineffective mode ISCVL3 = 1 VL3 function mode Caution Digital input mode PMmn = 0 PMmn = 1 Digital output mode Be sure to set the VL3 function mode before segment output starts (while SCOC bit of LCD mode register 1 (LCDM1) is 0). • CAPL/P126 and CAPH/P127 Table 14-6.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.8 LCD port function registers 0 to 4 (PFSEG0 to PFSEG4) These registers specify whether to use pins P10 to P17, P30 to P32, P41 to P43, P50 to P54, P60, P61, P70 to P74, P120, and P140 to P147 as port pins (other than segment output pins) or segment output pins. These registers are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-7.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER (a) Operation of ports that alternately function as SEGxx pins The functions of ports that also serve as segment output pins (SEGxx) can be selected by using the port mode control register (PMCxx), port mode register (PMxx), and LCD port function registers 0 to 4 (PFSEG0 to PFSEG4). • P10 to P12, P15 to P17, P30 to P32, P42, P43, P50 to P54, P60, P61, P70 to P74, P140, P141 (ports that do not serve as analog input pins (ANIxx)) Table 14-8.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER • P13, P14, P41, P120, P142 to P147 (ports that serve as analog input pins (ANIxx)) Table 14-9.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.3.9 Port mode registers 1, 3 to 7, 12, 14 (PM1, PM3 to PM7, PM12, PM14) These registers specify input/output of ports 1, 3 to 7, 12, and 14 in 1-bit units. When using the ports (such as P10/SCK00/SEG28, P120/ANI17/SEG25) to be shared with the segment output pin for segment output, set the port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.4 LCD Display Data Registers The LCD display data registers are mapped as shown in Table 14-10. The contents displayed on the LCD can be changed by changing the contents of the LCD display data registers. Table 14-10.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Table 14-10.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER To use the LCD display data register when the number of time slices is static, two, three, or four, the lower four bits and higher four bits of each address of the LCD display data register become an A-pattern area and a B-pattern area, respectively. The correspondences between A-pattern area data and COM signals are as follows: bit 0 ⇔ COM0, bit 1 ⇔ COM1, bit 2 ⇔ COM2, and bit 3 ⇔ COM3.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.5.1 A-pattern area and B-pattern area data display When BLON = LCDSEL = 0, A-pattern area (lower four bits of the LCD display data register) data will be output as the LCD display register. When BLON = 0, and LCDSEL = 1, B-pattern area (higher four bits of the LCD display data register) data will be output as the LCD display register. See 14.4 LCD Display Data Registers about the display area. 14.5.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.6 Setting the LCD Controller/Driver Set the LCD controller/driver using the following procedure. Caution To operate the LCD controller/driver, be sure to follow procedures (1) to (4). Unless these procedures are observed, the operation will not be guaranteed. (1) External resistance division method during normal liquid crystal waveform display Figure 14-18.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER (2) Internal voltage boosting method during normal liquid crystal waveform display Figure 14-19. Internal Voltage Boosting Method Setting Procedure During Normal Liquid Crystal Waveform Display Cautions 1. Wait until the setup time has elapsed even if not changing the setting of the VLCD register. 2. For the specifications of the reference voltage setup time and voltage boosting wait time, see CHAPTER 30 or 31 ELECTRICAL SPECIFICATIONS.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER (3) Capacitor split method during normal liquid crystal waveform display Figure 14-20. Capacitor Split Method Setting Procedure During Normal Liquid Crystal Waveform Display START Select the display waveform (select waveform A or B), number of time slices, and bias method by using the LWAVE, LDTY2 to LDTY0, LBAS1, and LBAS0 bits of the LCDM0 register. MDSET1 and MDSET0 bits of LCDM0 register = 10B (Specify the capacitor split method.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.7 Operation stop procedure To stop the operation of the LCD while it is displaying waveforms, follow the steps shown in the flowchart below. The LCD stops operating when the LCDON bit of LCDM1 register and SCOC bit of the LCDM1 register are set to “0”. Figure 14-21. Operation Stop Procedure (a) During normal liquid crystal waveform (waveform A or B) display LCDON bit of LCDM1 register = 0 (Display data off. Segment pin outputs deselect signal.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.8 Supplying LCD Drive Voltages VL1, VL2, VL3, and VL4 The power supply voltages for the LCD driver can be produced through external resistance division, internal voltage boosting, or capacitor split. 14.8.1 External resistance division method Figure 14-22 shows examples of LCD drive voltage connection, corresponding to each bias method. Figure 14-22.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Caution The reference resistance “R” value for external resistance division is 10 kΩ to 1 MΩ. In addition, to stabilize the voltage of the VL1 to VL4 pins, connect a capacitor between each of pins VL1 to VL4 and the GND pin as needed. The reference capacitance is about 0.47 μF but it depends on the LCD panel used, the number of segment pins, the number of common pins, the frame frequency, and the operating environment.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.8.3 Capacitor split method RL78/L12 contains an internal voltage reduction circuit for generating LCD drive power supplies. The internal voltage reduction circuit and external capacitors (0.47 μF±30%) are used to generate an LCD drive voltage. Only 1/3 bias mode can be set for the capacitor split method.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.9 Common and Segment Signals 14.9.1 Normal liquid crystal waveform Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference becomes lower than VLCD. Applying DC voltage to the common and segment signals of an LCD panel causes deterioration.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER (2) Segment signals The segment signals correspond to the LCD display data register (see 14.4 LCD Display Data Registers). When the number of time slices is eight, bits 0 to 7 of each display data register are read in synchronization with COM0 to COM7, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (SEG4 to SEG38).
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER (3) Output waveforms of common and segment signals The voltages listed in Table 14-14 are output as common and segment signals. When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained. The other combinations of the signals correspond to the display off-voltage. Table 14-14.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-25 shows the common signal waveforms, and Figure 14-26 shows the voltages and phases of the common and segment signals. Figure 14-25.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-25.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-26. Voltages and Phases of Common and Segment Signals (1/3) (a) Static display mode (waveform A) Select Deselect VL4 VLCD Common signal VSS VL4 VLCD Segment signal VSS T T T: One LCD clock period (b) 1/2 bias method (waveform A) Select Deselect VL4 VL2 Common signal VLCD VSS VL4 Segment signal VL2 VLCD VSS T T T: One LCD clock period R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-26. Voltages and Phases of Common and Segment Signals (2/3) (c) 1/3 bias method (waveform A) Select Deselect VL4 VL2 VL1 Common signal VLCD VSS VL4 VL2 VL1 Segment signal VLCD VSS T T T: One LCD clock period (d) 1/3 bias method (waveform B) Select Deselect VL4 VL2 VL1 Common signal VLCD VSS VL4 VL2 VL1 Segment signal VLCD VSS T/2 T/2 T/2 T/2 T: One LCD clock period R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-26. Voltages and Phases of Common and Segment Signals (3/3) (e) 1/4 bias method (waveform A) Select Deselect Common signal VL4 VL3 VL2 VL1 VSS VLCD Segment signal VL4 VL3 VL3 VL1 VSS VLCD T T T: One LCD clock period (f) 1/4 bias method (waveform B) Select Deselect Common signal VL4 VL3 VL2 VL1 VSS VLCD Segment signal VL4 VL3 VL2 VL1 VSS VLCD T/2 T/2 T/2 T/2 T: One LCD clock period R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.10 Display Modes 14.10.1 Static display example Figure 14-28 shows how the three-digit LCD panel having the display pattern shown in Figure 14-27 is connected to the segment signals (SEG0 to SEG23) and the common signal (COM0). This example displays data “12.3” in the LCD panel. The contents of the display data register (F0400H to F0417H) correspond to this display. The following description focuses on numeral “2.” ( ) displayed in the second digit.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-28.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-29.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.10.2 Two-time-slice display example Figure 14-31 shows how the 6-digit LCD panel having the display pattern shown in Figure 14-30 is connected to the segment signals (SEG0 to SEG23) and the common signals (COM0 and COM1). This example displays data “12345.6” in the LCD panel. The contents of the display data register (F0400H to F0417H) correspond to this display. The following description focuses on numeral “3” ( ) displayed in the fourth digit.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Timing strobe Figure 14-31.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-32.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.10.3 Three-time-slice display example Figure 14-34 shows how the 8-digit LCD panel having the display pattern shown in Figure 14-33 is connected to the segment signals (SEG0 to SEG23) and the common signals (COM0 to COM2). This example displays data “123456.78” in the LCD panel. The contents of the display data register (addresses F0400H to F0417H) correspond to this display. The following description focuses on numeral “6.” ( ) displayed in the third digit.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-34.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-35.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-36.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.10.4 Four-time-slice display example Figure 14-38 shows how the 12-digit LCD panel having the display pattern shown in Figure 14-37 is connected to the segment signals (SEG0 to SEG23) and the common signals (COM0 to COM3). This example displays data “123456.789012” in the LCD panel. The contents of the display data register (addresses F0400H to F0417H) correspond to this display. The following description focuses on numeral “6.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-38. Example of Connecting Four-Time-Slice LCD Panel Timing strobe COM 3 COM 2 COM 1 2 3 4 5 6 7 Data memory address 8 9 A B C D E F F0410H 1 2 3 4 5 6 7 R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-39.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-39.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER 14.10.5 Eight-time-slice display example Figure 14-41 shows how the 15x8 dot LCD panel having the display pattern shown in Figure 14-40 is connected to the segment signals (SEG4 to SEG18) and the common signals (COM0 to COM7). This example displays data “123” in the LCD panel. The contents of the display data register (addresses F0404H to F0412H) correspond to this display. The following description focuses on numeral “3.” ( ) displayed in the first digit.
Data memory address F0404H 5 6 7 8 9 A B C D E F0410H F 1 2 R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-42. Eight-Time-Slice LCD Drive Waveform Examples Between SEG4 and Each Common Signals (1/4 Bias Method) (1/2) (a) Waveform A 1 frame Internal signal LCD clock COM0 VL4 VL3 VL2 VL1 VSS COM1 VL4 VL3 VL2 VL1 VSS COM2 VL4 VL3 VL2 VL1 VSS .. . COM7 VL4 VL3 VL2 VL1 VSS SEG4 VL4 VL3 VL2 VL1 VSS Lights COM0-SEG4 Extinguishes +VL4 +VL3 +VL2 +VL1 0 VL1 VL2 VL3 VL4 COM0-SEG4 COM1-SEG4 Extinguishes COM1-SEG4 R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER Figure 14-42. Eight-Time-Slice LCD Drive Waveform Examples Between SEG4 and Each Common Signals (1/4 Bias Method) (2/2) (b) Waveform B 1 frame Internal signal LCD clock COM0 VL4 VL3 VL2 VL1 VSS COM1 VL4 VL3 VL2 VL1 VSS COM2 VL4 VL3 VL2 VL1 VSS .. .
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. • 16 bits × 16 bits = 32 bits (Unsigned) • 16 bits × 16 bits = 32 bits (Signed) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Signed) • 32 bits ÷ 32 bits = 32 bits, 32-bits remainder (Unsigned) 15.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 15-1.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.2.1 Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.2.2 Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode. The MDBH and MDBL registers can be set by a 16-bit manipulation instruction.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.2.3 Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode. The MDCH and MDCL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 15-4.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). 15.3.1 Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Notes 1. Bits 1 and 2 are read-only bits. 2. The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively. Cautions 1.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.4 Operations of Multiplier and Divider/Multiply-Accumulator 15.4.1 Multiplication (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.4.2 Multiplication (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.4.3 Multiply-accumulation (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH). <4> Set the multiplicand to multiplication/division data register A (L) (MDAL).
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 15-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 × 3 + 3 = 9 → 32767 × 2 + 4294901762 = 0 (over flow generated)) Operation clock <1> MDUC 00H 40H 44H MDSM L 0000H 0000H MDCH 0000H MDCL FFFFH 0003H 0009H 0000H 0000H 0002H <8>, <9> MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H 0002H 7FFFH 0003H 0002H 0000H 0006H 0000H FFFEH <10> INTMD MACOF MACSF L <2> <3> <4> R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.4.4 Multiply-accumulation (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL).
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 15-9. Timing Diagram of Multiply-Accumulation (signed) Operation (2 × 3 + (−4) = 2 → 32767 × (−1) + (−2147483647) = −2147450882 (overflow occurs.
RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 15.4.5 Division operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL). <4> Set the divisor (higher 16 bits) to multiplication/division data register B (H) (MDBH).
R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 16 DMA CONTROLLER CHAPTER 16 DMA CONTROLLER The RL78/L12 has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 16-1. Configuration of DMA Controller Item Configuration • DMA SFR address registers 0, 1 (DSA0, DSA1) Address registers • DMA RAM address registers 0, 1 (DRA0, DRA1) Count register • DMA byte count registers 0, 1 (DBC0, DBC1) Control registers • DMA mode control registers 0, 1 (DMC0, DMC1) • DMA operation control register 0, 1 (DRC0, DRC1) 16.2.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.2.2 DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers can be set to this register. Set the lower 16 bits of the RAM address. This register is automatically incremented when DMA transfer has been started.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.2.3 DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times). Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn register during DMA transfer, the remaining number of times of transfer can be learned.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. • DMA mode control register n (DMCn) • DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0, 1) R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.3.1 DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA. Rewriting bits 6, 5, and 3 to 0 of the DMCn register is prohibited during operation (when DSTn = 1). The DMCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 16 DMA CONTROLLER Figure 16-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 0 or 1) IFCn IFCn IFCn IFCn 3 2 1 0 Trigger signal 0 0 0 0 − Selection of DMA start source Note Trigger contents Disables DMA transfer by interrupt. (Only software trigger is enabled.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1). The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-5.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.4 Operation of DMA Controller 16.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn).
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.5 Example of Setting of DMA Controller 16.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. • Consecutive transmission of CSI00 (256 bytes) • DMA channel 0 is used for DMA transfer. • DMA start source: INTCSI00 (software trigger (STG0) only for the first start source) • Interrupt of CSI00 is specified by IFC03 to IFC00 = 0110B.
RL78/L12 CHAPTER 16 DMA CONTROLLER Figure 16-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 44H DRA0 = FB00H DBC0 = 0100H DMC0 = 48H Setting for CSI transfer DST0 = 1 DMA0 is started. STG0 = 1 INTCSI00 occurs. User program processing DMA0 transfer CSI transmission Occurrence of INTDMA0 DST0 = 0Note DEN0 = 0 RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. • Consecutive capturing of A/D conversion results. • DMA channel 1 is used for DMA transfer. • DMA start source: INTAD • Interrupt of A/D is specified by IFC13 to IFC10 = 0001B. • Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register (ADCR) to 512 bytes of FFCE0H to FFEDFH of RAM.
RL78/L12 CHAPTER 16 DMA CONTROLLER Figure 16-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs. User program processing DMA1 transfer INTDMA1 occurs. DST1 = 0Note DEN1 = 0 RETI Hardware operation End Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN1 flag is enabled only when DST1 = 0.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. • Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception. • DMA channel 0 is used for DMA transfer. • DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.
RL78/L12 CHAPTER 16 DMA CONTROLLER Figure 16-9. Example of Setting for UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H DRA0 = FE00H DBC0 = 0040H DMA0 is started. DMC0 = 00H STG0 = 1 DMA0 transfer P10 = 1 Setting for UART reception P10 = 0 DST0 = 1 INTSR0 occurs. RETI User program processing INTDMA0 occurs. DST0 = 0 DEN0 = 0Note RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
RL78/L12 CHAPTER 16 DMA CONTROLLER Figure 16-11.
RL78/L12 CHAPTER 16 DMA CONTROLLER 16.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority are DMA channel 0 > DMA channel 1.
RL78/L12 CHAPTER 16 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions. • CALL !addr16 • CALL $!addr20 • CALL !!addr20 • CALL rp • CALLT [addr5] • BRK • Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, MK0L, MK0H, MK1L, MK1H, MK2L, PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, PR12L, and PSW each.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS CHAPTER 17 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product. 32-pin 44-pin 48-pin 52-pin 64-pin Maskable External 4 6 7 7 9 interrupts Internal 23 23 23 23 23 17.1 Interrupt Function Types The following two types of interrupt functions are used.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (2/3) Basic Configuration Note 2 Type 64-pin 52-pin 48-pin 44-pin 32-pin Default Priority Interrupt Type (A) √ √ √ √ √ 0028H √ √ √ √ √ End of timer channel 02 count or capture 002AH √ √ √ √ √ End of timer channel 03 count or capture 002CH √ √ √ √ √ Internal/ External Interrupt Source Name Trigger 0026H Note 1 Vector Table Address Maskable Notes 1.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (3/3) Basic Configuration Note 2 Type 64-pin 52-pin 48-pin 44-pin 32-pin BRK Execution of BRK instruction − 007EH (D) √ √ √ √ √ − 0000H − Default Priority Interrupt Type Interrupt Source Internal/ External Vector Table Address Note 1 Software − Reset − Notes 1.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-2.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-2.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Cautions 1. The available registers and bits differ depending on the product. For details about the registers and bits available for each product, see Table 17-2. Be sure to set bits that are not available to the initial value. 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as “IF0L.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. The MK0L, MK0H, MK1L, MK1H, and MK2L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L and MK0H registers, and the MK1L and MK1H registers are combined to form 16-bit registers MK0 and MK1, they can be set by a 16-bit memory manipulation instruction.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, PR12L) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, or 2L).
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-4.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) These registers specify the valid edge for INTP0 to INTP7. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 17-5.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-3.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI).
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, jump to interrupt servicing Instruction Interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/fCLK (fCLK: CPU clock) Figure 17-9.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-5.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing IE = 0 EI INTyy servicing IE = 0 IE = 0 EI INTxx (PR = 11) INTzz servicing EI INTyy (PR = 10) INTzz (PR = 01) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (2/2) Example 3.
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. • MOV PSW, #byte • MOV PSW, A • MOV1 PSW. bit, CY • SET1 PSW. bit • CLR1 PSW. bit • RETB • RETI • POP PSW • BTCLR PSW.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION CHAPTER 18 KEY INTERRUPT FUNCTION 18.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by inputting a rising edge/falling edge to the key interrupt input pins (KR0 to KR3). Table 18-1. Assignment of Key Interrupt Detection Pins Key interrupt input pins Key return mode registers (KRM) KR0 KRM0 KR1 KRM1 KR2 KRM2 KR3 KRM3 R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION 18.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 18-2. Configuration of Key Interrupt Item Configuration Control register Key return control register (KRCTL) Key return mode register 0 (KRM0) Port mode registers 1, 3, 7, 14 (PM1, PM3, PM7, PM14) Note Note The port mode registers (PMxx) to be set differ depending on the product. For details, see 18.3.4 Port mode registers 1, 3, 7, 14 (PM1, PM3, PM7, PM14).
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION 18.3 Register Controlling Key Interrupt The key interrupt function is controlled by the following five registers: • Key return control register (KRCTL) • Key return mode register 0 (KRM0) • Key return flag register (KRF) • Port mode registers 1, 3, 7, and 14 (PM1, PM3, PM7, PM14) Note Note The port mode registers (PMxx) to be set differ depending on the product. For details, see 18.3.4 Port mode registers 1, 3, 7, 14 (PM1, PM3, PM7, PM14). 18.3.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION 18.3.2 Key return mode register 0 (KRM0) This register sets the key interrupt mode. The KRM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 18-3.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION 18.3.4 Port mode registers 1, 3, 7, 14 (PM1, PM3, PM7, PM14) These registers set the input and output of port 1, 3, 7, 14 in 1-bit units. The presence or absence of key input pins depends on the product. When using the key interrupt function, set the following port mode registers according to the product used.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION 18.4 Key Interrupt Operation 18.4.1 When not using the key interrupt flag (KRMD = 0) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR3). The channel to which the valid edge was input can be identified by reading the port register and checking the port level after the key interrupt (INTKR) is generated.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION 18.4.2 When using the key interrupt flag (KRMD = 1) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR3). The channels to which the valid edge was input can be identified by reading the key return flag register (KRF) after the key interrupt (INTKR) is generated. If the KRMD bit is set to 1, the INTKR signal is cleared by clearing the corresponding bit in the KRF register.
RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 18-9 below. A falling edge is also input to the KR1 and KR3 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KRF1 bit is set when the KRF0 bit is cleared. A key interrupt (INTKR) is therefore generated one clock (fCLK) after the KRF0 bit is cleared (<1> in the figure).
RL78/L12 CHAPTER 19 STANDBY FUNCTION CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function and Configuration 19.1.1 Standby function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
RL78/L12 CHAPTER 19 STANDBY FUNCTION 19.2 Registers controlling standby function The registers which control the standby function are described below. • Subsystem clock supply mode control register (OSMC) • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For details of registers described above, see CHAPTER 5 CLOCK GENERATOR.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Table 19-1.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Table 19-1.
RL78/L12 CHAPTER 19 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 19-1.
RL78/L12 CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-2.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Figure 19-2.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Table 19-2.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Cautions 1. To stop the low-speed on-chip oscillator clock in the STOP mode, must previously be set an option byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0). 2.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Figure 19-3. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt request STOP instruction Standby release signal Note 1 Status of CPU High-speed system clock (X1 oscillation) Notes 1. 2.
RL78/L12 CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-4.
RL78/L12 CHAPTER 19 STANDBY FUNCTION 19.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSI00, UART0, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock. When using CSI00 or UART0 in the SNOOZE mode, set the SWCm bit of the serial standby control register m (SSCm) to 1 immediately before switching to the STOP mode. For details, see 12.3 Registers Controlling Serial Array Unit.
RL78/L12 CHAPTER 19 STANDBY FUNCTION Table 19-3.
RL78/L12 CHAPTER 20 RESET FUNCTION CHAPTER 20 RESET FUNCTION The following seven operations are available to generate a reset signal.
R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 Set Clear Clear Set WDTRF 2. LVIS: Voltage detection level register Remarks 1. LVIM: Voltage detection register Caution An LVD circuit internal reset does not reset the LVD circuit.
RL78/L12 CHAPTER 20 RESET FUNCTION 20.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts. Figure 20-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software.
RL78/L12 Notes 1. CHAPTER 20 RESET FUNCTION When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummyoutput as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software. 2. Reset times (times for release from the external reset state) After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use. 0.
RL78/L12 CHAPTER 20 RESET FUNCTION 20.2 States of Operation During Reset Periods Table 20-1 shows the states of operation during reset periods. Table 20-2 shows the states of the hardware after receiving a reset signal. Table 20-1. States of Operation During Reset Period Item During Reset Period System clock Main system clock Subsystem clock Clock supply to the CPU is stopped.
RL78/L12 Note CHAPTER 20 RESET FUNCTION P40 and P130 become the following state. • P40: High-impedance during the external reset period or reset period by the POR. High level during other types of reset (connected to the internal pull-up resistor).
RL78/L12 CHAPTER 20 RESET FUNCTION 20.3 Register for Confirming Reset Source 20.3.1 Reset Control Flag Register (RESF) Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags.
RL78/L12 CHAPTER 20 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 20-3. Table 20-3.
RL78/L12 CHAPTER 20 RESET FUNCTION Figure 20-5. Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and store the value of the RESF register in any RAM.
RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT CHAPTER 21 POWER-ON-RESET CIRCUIT 21.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. • Generates internal reset signal at power on. The reset signal is released when the supply voltage (VDD) exceeds the detection voltage (VPOR). Note that the reset state must be retained until the operating voltage becomes in the range defined in 30.4 or 31.4 AC Characteristics.
RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT 21.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-reset Circuit VDD VDD + Internal reset signal − Reference voltage source 21.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) (1) When the externally input reset signal on the RESET pin is used Supply voltage (VDD) Note 5 Note 5 Lower limit voltage for guaranteed operation VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (VDD) Note 3 VLVDH VLVDL Lower limit voltage for guaranteed operation VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
RL78/L12 CHAPTER 21 POWER-ON-RESET CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (3) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1) Supply voltage (VDD) VLVD Lower limit voltage for guaranteed operation VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR CHAPTER 22 VOLTAGE DETECTOR 22.1 Functions of Voltage Detector The operation mode and detection voltages (VLVDH, VLVDL, VLVD) for the voltage detector is set by using the option byte (000C1H). The voltage detector (LVD) has the following functions. • The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL), and generates an internal reset or internal interrupt signal.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 22-1. Figure 22-1.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-2.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H/01H/81H Note1. Figure 22-3.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR Table 22-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (1/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt & reset mode) Detection voltage VLVDH Option byte setting value VLVDL VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising edge Falling edge Falling edge 1.77 V 1.73 V 1.63 V 1 0 1.88 V 1.84 V 0 1 2.92 V 2.86 V 0 0 1.98 V 1.94 V 1 0 2.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR Table 22-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (2/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detection voltage Option byte setting value VLVD Rising edge VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Falling edge 1.67 V 1.63 V 0 0 1 1 1.77 V 1.73 V 0 0 1 0 1.88 V 1.84 V 0 1 1 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.4 Operation of Voltage Detector 22.4.1 When used as reset mode Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. The operation is started in the following initial setting state when the reset mode is set.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR Figure 22-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (VDD) VLVD Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.4.2 When used as interrupt mode Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt mode is set.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR Figure 22-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Note 2 Supply voltage (VDD) Note 2 VLVD Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time HNote 1 LVIMK flag (interrupt MASK) (set by software) Cleared by software Cleared LVIF flag LVIMD flag H LVILV flag INTLVI LVIIF flag LVD reset signal POR reset signal Internal reset signal Notes 1. 2.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.4.3 When used as interrupt and reset mode • When starting operation Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH, VLVDL) by using the option byte 000C1H. Start in the following initial setting state. • Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)).
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR Figure 22-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of VDD becomes VDD ≥ VLVDH, clear LVIMD bit to 0, and the MCU shift to normal operation. Supply voltage (VDD) VLVDH VLVDL Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
RL78/L12 Notes 1. 2. CHAPTER 22 VOLTAGE DETECTOR The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 22-7 Processing Procedure After an Interrupt Is Generated. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR Figure 22-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of VDD is VDD < VLVIH after releasing the mask, a reset is generated because of LVIMD = 1 (reset mode). Supply voltage (VDD) VLVDH VLVDL Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
RL78/L12 Notes 1. 2. CHAPTER 22 VOLTAGE DETECTOR The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 22-7 Processing Procedure After an Interrupt Is Generated. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Figure 22-7.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR 22.5 Cautions for Voltage Detector (1) Checking reset source When a reset occurs, check the reset source by using the following method. Figure 22-8.
RL78/L12 CHAPTER 22 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has been generated. In the same way, there is also some delay from the time LVD detection voltage (VLVD) ≤ supply voltage (VDD) until the time LVD reset has been released (see Figure 22-9). Figure 22-9.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS CHAPTER 23 SAFETY FUNCTIONS 23.1 Overview of Safety Functions The following safety functions are provided in the RL78/L12 to comply with the IEC60730 and IEC61508 safety standards. These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is detected. (1) Flash memory CRC operation function (high-speed CRC, general-purpose CRC) This detects data errors in the flash memory by performing CRC operations.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.2 Registers Used by Safety Functions The safety functions use the following registers for each function.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.1.1 Flash memory CRC control register (CRC0CTL) This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 23-1.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.1.2 Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 23-2.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS Figure 23-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ; Set CRC operation range. ; Copy the HALT and RET instructions to the ; RAM to execute in the RAM. ; Initialize the 10 bytes after the RET instruction.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.2 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. In the RL78/L12, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.2.2 CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register. The CRCD register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 23-5.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.3 RAM parity error detection function The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/L12’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs. 23.3.3.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS Figure 23-8. Flowchart of RAM Parity Check Start of check RPERF = 1Note Yes No RPERDIS = 1 Disable parity error reset. Check RAM. Check RAM. Parity error generated? No RPEF = 1 RPERDIS = 0 Note Yes Parity error generation checked No Yes Internal error generated Read RAM. Normal operation Enable parity error reset. RAM failure processing To check internal reset status using a RAM parity error, see CHAPTER 20 RESET FUNCTION.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space. If the RAM guard function is specified, writing to the specified RAM space is disabled, but reading from the space can be carried out as usual. 23.3.4.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed. The illegal memory access detection function applies to the areas indicated by NG in Figure 23-11. Figure 23-11.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.6.1 Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 23-12.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (fCLK) and measuring the pulse width of the input signal to channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.7.1 Timer input select register 0 (TIS0) This register is used to select the timer input of channel 1. By selecting the low-speed on-chip oscillator clock for the timer input, its pulse width can be measured to determine whether the proportional relationship between the low-speed on-chip oscillator clock and the timer operation clock is correct. The TIS0 register can be set by an 8-bit memory manipulation instruction.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function checks whether or not the A/D converter is operating normally by executing A/D conversions of the A/D converter’s positive and negative reference voltages, analog input channel (ANI), temperature sensor output voltage, and the internal reference voltage. For details of the check method, see the safety function (A/D test) application note (R01AN0955).
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS Figure 23-15. Configuration of A/D Test Function ADISS ADS4 to ADS0 ANI0/AVREFP ANI1/AVREFM ANIxx ADTES1, ADTES0 ANIxx Temperature sensor Note Internal reference voltage (1.45 V) Positive reference voltage of AD converter VDD ADREFP1 ADREFP0 A/D converter Negative reference voltage of AD converter VSS ADREFM Note This setting can be used only in HS (high-speed main) mode. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.8.1 A/D test register (ADTES) This register is used to select the A/D converter’s positive reference voltage, A/D converter’s negative reference voltage, analog input channel (ANIxx), temperature sensor output voltage, or internal reference voltage (1.45 V) as the target of A/D conversion. When using the A/D test function, specify the following settings: • Select negative reference voltage as the target of A/D conversion for zero-scale measurement.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS 23.3.8.2 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output /internal reference voltage (1.45 V). The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 23-17.
RL78/L12 CHAPTER 23 SAFETY FUNCTIONS output/internal reference voltage output is selected (example for software trigger mode and one-shot conversion mode). 9. If a transition is made to STOP mode or a transition is made to HALT mode during CPU operation with subsystem clock, do not set ADISS to 1. When ADISS is 1, the A/D converter reference voltage current (IADREF) shown in 30.3.2 or 31.3.2 Supply current characteristics is added. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 24 REGULATOR CHAPTER 24 REGULATOR 24.1 Regulator Overview The RL78/L12 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
RL78/L12 CHAPTER 25 OPTION BYTE CHAPTER 25 OPTION BYTE 25.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/L12 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set. When using the product, be sure to set the following functions by using the option bytes.
RL78/L12 CHAPTER 25 OPTION BYTE 25.1.2 On-chip debug option byte (000C3H) Control of on-chip debug operation • On-chip debug operation is disabled or enabled. Handling of data of flash memory in case of failure in on-chip debug security ID authentication • Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication. R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 25 OPTION BYTE 25.2 Format of User Option Byte The format of user option byte is shown below. Figure 25-1. Format of User Option Byte (000C0H) Address: 000C0H 7 6 5 4 3 2 1 0 WDTINT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTINT Use of interval interrupt of watchdog timer 0 Interval interrupt is not used. 1 Interval interrupt is generated when 75% + 1/2fIL of the overflow time is reached.
RL78/L12 CHAPTER 25 OPTION BYTE Figure 25-2. Format of User Option Byte (000C1H) (1/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt & reset mode) Detection voltage VLVDH Option byte setting value VLVDL Rising Falling Falling edge edge edge 1.77 V 1.73 V 1.63 V 1.88 V 2.92 V 1.98 V 1.94 V 2.09 V 3.13 V 2.61 V 2.55 V 2.71 V 2.65 V 3.75 V 3.67 V 2.92 V 2.86 V 3.02 V 2.96 V 4.06 V 3.
RL78/L12 CHAPTER 25 OPTION BYTE Figure 25-2. Format of User Option Byte (000C1H) (2/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detection voltage Option byte setting value VLVD VPOC2 Rising edge Falling edge 1.67 V 1.63 V 1.77 V VPOC1 LVIS1 LVIS0 0 0 1 1 1.73 V 0 0 1 0 1.88 V 1.84 V 0 1 1 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.45 V 1 0 1 1 2.61 V 2.
RL78/L12 CHAPTER 25 OPTION BYTE Figure 25-3. Format of Option Byte (000C2H) Address: 000C2H 7 6 5 4 3 2 1 0 CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Operating voltage frequency range range 0 0 LV (low voltage main) mode 1 to 4 MHz 1.6 to 5.5 V 1 0 LS (low speed main) mode 1 to 8 MHz 1.8 to 5.5 V 1 1 HS (high speed main) mode 1 to 16 MHz 2.4 to 5.5 V 1 to 24 MHz 2.7 to 5.
RL78/L12 CHAPTER 25 OPTION BYTE 25.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 25-4. Format of On-chip Debug Option Byte (000C3H) Address: 000C3H 7 6 5 4 3 2 1 0 OCDENSET 0 0 0 0 1 0 OCDERSD OCDENSET OCDERSD 0 0 Disables on-chip debug operation. 0 1 Setting prohibited 1 0 Enables on-chip debugging.
RL78/L12 CHAPTER 25 OPTION BYTE 25.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions exist in the source, as mentioned below. A software description example of the option byte setting is shown below.
RL78/L12 CHAPTER 26 FLASH MEMORY CHAPTER 26 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data. FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAM 1 to 1.
RL78/L12 CHAPTER 26 FLASH MEMORY The following methods for programming the flash memory are available. The code flash memory can be rewritten to through serial programming using a flash memory programmer or an external device (UART communication), or through self-programming. • Serial programming using flash memory programmer (see 26.1) Data can be written to the flash memory on-board or off-board by using a dedicated flash memory programmer.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.1 Writing to Flash Memory by Using Flash Memory Programmer The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78 microcontroller. • PG-FP5, FL-PR5 • E1 on-chip debugging emulator Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
RL78/L12 CHAPTER 26 FLASH MEMORY Table 26-1. Wiring Between RL78/L12 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Signal Name I/O Pin Name Pin Function Pin No.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.1.1 Programming Environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 26-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 VDD E1 EVDDNote RS-232C VSS, EVSS USB RESET RL78 Dedicated flash TOOL0 (dedicated single-line UART) microcontroller memory programmer Host machine Note 64-pin products only.
RL78/L12 CHAPTER 26 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See the manual of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 26-2.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.2.2 Communication Mode Communication between the external device and the RL78 microcontroller is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78 microcontroller. Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps Figure 26-4.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.3.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to either to VDD or EVDD, or VSS or EVSS, via a resistor. 26.3.4 REGC pin Connect the REGC pin to GND via a capacitor (0.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.4 Serial Programming Method 26.4.1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 26-6. Code Flash Memory Manipulation Procedure Start Controlling TOOL0 pin and RESET pin Flash memory programming mode is set Manipulate code flash memory End? No Yes End R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.4.2 Flash memory programming mode To rewrite the contents of the code flash memory through serial programming, specify the flash memory programming mode. To enter the mode, set as follows. Connect the RL78 microcontroller to a dedicated flash memory programmer. Communication from the dedicated flash memory programmer is performed to automatically switch to the flash memory programming mode.
RL78/L12 CHAPTER 26 FLASH MEMORY There are two flash memory programming modes: wide voltage mode and full speed mode. The supply voltage value applied to the microcontroller during write operations and the setting information of the user option byte for setting of the flash memory programming mode determine which mode is selected. When a dedicated flash memory programmer is used for serial programming, setting the voltage on GUI selects the mode automatically. Table 26-5.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.4.3 Selecting communication mode Communication modes of the RL78 microcontroller are as follows. Table 26-6.
RL78/L12 CHAPTER 26 FLASH MEMORY Product information (such as product name and firmware version) can be obtained by executing the “Silicon Signature” command. Table 26-8 is a list of signature data and Table 26-9 shows an example of signature data. Table 26-8.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) The following shows the processing time for each command (reference value) when PG-FP5 is used as a dedicated flash memory programmer. Table 26-10. Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) PG-FP5 Command Code Flash 8 Kbytes 16 Kbytes 32 Kbytes Erasing 1s 1.5 s 1.5 s Writing 1.5 s 1.5 s 2s Verification 1.5 s 1.5 s 1.5 s Writing after erasing 1.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.6 Self-Programming The RL78 microcontroller supports a self-programming function that can be used to rewrite the code flash memory via a user program. Because this function allows a user application to rewrite the code flash memory by using the flash selfprogramming library, it can be used to upgrade the program in the field. Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock. 2.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.6.1 Self-programming procedure The following figure illustrates a flow for rewriting the code flash memory by using a flash self-programming library. Figure 26-8.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.6.2 Flash shield window function The flash shield window function is provided as one of the security functions for self-programming. It disables writing to and erasing areas outside the range specified as a window only during self-programming. The window range can be set by specifying the start and end blocks. The window range can be set or changed during both serial programming and self-programming.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.7 Security Settings The RL78 microcontroller supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. • Disabling block erase Execution of the block erase command for a specific block in the flash memory is prohibited during serial programming.
RL78/L12 CHAPTER 26 FLASH MEMORY Table 26-12. Relationship between Enabling Security Function and Command (1) During serial programming Valid Security Executed Command Block Erase Write Note Prohibition of block erase Blocks cannot be erased. Can be performed. Prohibition of writing Blocks can be erased. Cannot be performed. Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Note Confirm that no data has been written to the write area.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.8 Data Flash 26.8.1 Data flash overview An overview of the data flash memory is provided below. • The user program can rewrite the data flash memory by using the flash data library. For details, refer to RL78 Family Flash Data Library User’s Manual. • The data flash memory can also be rewritten to through serial programming using the dedicated flash memory programmer or an external device. • The data flash can be erased in 1-block (1-Kbyte) units.
RL78/L12 CHAPTER 26 FLASH MEMORY 26.8.3 Procedure for accessing data flash memory The data flash memory is stopped after a reset ends. To access the data flash, make initial settings according to the following procedure. <1> Set bit 0 (DFLEN) of the data flash control register (DFLCTL) to 1. <2> Wait for the setup to finish for software timer, etc. The time setup takes differs for each flash operation mode for the main clock.
RL78/L12 CHAPTER 27 ON-CHIP DEBUG FUNCTION CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.1 Connecting E1 On-chip Debugging Emulator The RL78 microcontroller uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1 on-chip debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution The RL78 microcontroller has an on-chip debug function, which is provided for development and evaluation.
RL78/L12 CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.2 On-Chip Debug Security ID The RL78 microcontroller has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 25 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content. Table 27-1. On-Chip Debug Security ID Address 000C4H to 000CDH On-Chip Debug Security ID Any ID code of 10 bytes 27.
RL78/L12 CHAPTER 27 ON-CHIP DEBUG FUNCTION Figure 27-2.
RL78/L12 CHAPTER 28 BCD CORRECTION CIRCUIT CHAPTER 28 BCD CORRECTION CIRCUIT 28.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ). 28.
RL78/L12 CHAPTER 28 BCD CORRECTION CIRCUIT 28.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1> The BCD code value to which addition is performed is stored in the A register.
RL78/L12 CHAPTER 28 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
RL78/L12 CHAPTER 29 INSTRUCTION SET CHAPTER 29 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Family User’s Manual: software (R01US0015). R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 29 INSTRUCTION SET 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.
RL78/L12 CHAPTER 29 INSTRUCTION SET 29.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 29-2.
RL78/L12 CHAPTER 29 INSTRUCTION SET 29.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 29-3. Symbols in “Flag” Column Symbol Change of Flag Value (Blank) Unchanged 0 Cleared to 0 1 Set to 1 × R Set/cleared according to the result Previously saved value is restored 29.1.
RL78/L12 CHAPTER 29 INSTRUCTION SET 29.2 Operation List Table 29-5. Operation List (1/17) Instruction Mnemonic Group 8-bit data transfer Notes 1. 2. 3.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Group 8-bit data transfer Notes 1.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Group 8-bit data XCH transfer ONEB CLRB MOVS 16-bit MOVW data Clocks Note 1 Note 2 2. 3.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Group 16-bit ADDW operation SUBW CMPW Multiply Notes 1.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Group Bit Clocks Clocks Note 1 Note 2 Flag Z AC CY CY, A.bit 2 1 − CY ← CY ∨ A.bit × CY, PSW.bit 3 1 − CY ← CY ∨ PSW.bit × CY, saddr.bit 3 1 − CY ← CY ∨ (saddr).bit × CY, sfr.bit 3 1 − CY ← CY ∨ sfr.bit × CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit × CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit × A.bit 2 1 − A.bit ← 1 PSW.bit 3 4 − PSW.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5.
RL78/L12 CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Group Conditional Clocks Note 1 BF saddr.bit, $addr20 branch sfr.bit, $addr20 A.bit, $addr20 PSW.bit, $addr20 [HL].bit, $addr20 ES:[HL].bit, Clocks Note 2 Z 3/5 Note3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 0 3/5 Note3 − PC ← PC + 4 + jdisp8 if sfr.bit = 0 3/5 Note3 − PC ← PC + 3 + jdisp8 if A.bit = 0 3/5 Note3 − PC ← PC + 4 + jdisp8 if PSW.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85°C)" and "G: Industrial applications (with TA = -40 to +85°C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) Parameter Symbols Supply voltage (1/3) Conditions Ratings Unit VDD VDD = EVDD −0.5 to +6.5 V EVDD VDD = EVDD −0.5 to +6.5 V −0.5 to +0.3 V EVSS REGC pin input voltage VIREGC −0.3 to +2.8 REGC V Note 1 and −0.3 to VDD + 0.3 Input voltage VI1 P70 to P74, P120, P125 to P127,P140 to P147 VI2 −0.3 to EVDD +0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Absolute Maximum Ratings (TA = 25°C) Parameter LCD voltage (2/3) Symbols VL1 Conditions VL1 voltage Note 1 Ratings Unit −0.3 to +2.8 V and −0.3 to VL4 + 0.3 VL2 VL3 VL4 VLCAP VLOUT VL2 voltage Note 1 −0.3 to VL4 + 0.3 Note 2 V VL3 voltage Note 1 −0.3 to VL4 + 0.3 Note 2 V VL4 voltage Note 1 CAPL, CAPH voltage COM0 to COM7, External resistance division V −0.3 to VL4 + 0.3 Note 2 V −0.3 to VDD + 0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Absolute Maximum Ratings (TA = 25°C) Parameter Output current, high Symbols IOH1 (3/3) Conditions Per pin P10 to P17, P30 to P32, Ratings Unit −40 mA −70 mA −100 mA P40 to P43, P50 to P54, P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of all pins P10 to P14, P40 to P43, P120, −170 mA P130, P140 to P147 P15 to P17, P30 to P32, P50 to P54, P70 to P74, P125 to P127 IOH2 Per pin P20, P21 Total of all pins Ou
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.2 Oscillator Characteristics 30.2.1 X1, XT1 oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Resonator X1 clock oscillation frequency Ceramic resonator/ (fX) Note Conditions MIN. TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD ≤ 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.7 V 1.0 8.0 MHz 1.6 V ≤ VDD <1.8 V 1.0 4.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.3 DC Characteristics 30.3.1 Pin characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output current, Note 1 high IOH1 Conditions (1/5) MIN. TYP.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions (2/5) MIN. TYP.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Input voltage, Symbol VIH1 Conditions P10 to P17, P30 to P32, P40 to P43, (3/5) MIN. TYP. MAX. Unit Normal input buffer 0.8EVDD EVDD V TTL input buffer 2.2 EVDD V 2.0 EVDD V 1.50 EVDD V P50 to P54, P70 to P74, P120, high P125 to P127, P140 to P147 VIH2 P10, P11, P15, P16 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 3.3 V ≤ EVDD < 4.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output voltage, VOH1 high Conditions (4/5) MIN. P10 to P17, P30 to P32, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V, EVDD−1.5 P50 to P54, P70 to P74, P120, IOH1 = −10 mA P125 to P127, P130, P140 to P147 TYP. MAX. Unit V 4.0 V ≤ EVDD ≤ 5.5 V, EVDD−0.7 V IOH1 = −3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, EVDD−0.6 V IOH1 = −2.0 mA 1.8 V ≤ EVDD ≤ 5.5 V, EVDD−0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Input leakage Symbol ILIH1 Conditions P10 to P17, P30 to P32, (5/5) MIN. TYP. MAX.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.3.2 Supply current characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Supply current Symbol IDD1 Conditions Operating mode Note 1 HS (highspeed main) Note 5 mode fIH = 24 MHz LS (lowspeed main) Note 5 mode fIH = 8 MHz LV (lowfIH = 4 MHz voltage main) Note 5 mode HS (highspeed main) Note 5 mode MIN. Note 3 Basic VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Supply current I DD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) Note 7 mode fIH = 24 MHz fIH = 16 MHz LS (lowspeed main) Note 7 mode fIH = 8 MHz LV (lowvoltage main) mode fIH = 4 MHz (2/3) MIN. Note 4 Note 4 TYP. MAX. Unit VDD = 5.0 V 0.44 1.28 mA VDD = 3.0 V 0.44 1.28 mA VDD = 5.0 V 0.40 1.00 mA VDD = 3.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Low-speed on- Symbol IFIL Conditions (3/3) MIN. Note 1 TYP. MAX. Unit 0.20 μA 0.08 μA 0.08 μA 0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator).
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.4 AC Characteristics 30.4.1 Basic operation (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions MIN. μs μs 1 μs 1 μs 31.3 μs 1 1 μs μs μs 0.125 1 μs 0.125 1.8 V ≤ VDD ≤ 5.5 V 28.5 In the self HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167 programmin main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 g mode LV (low voltage 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 Cycle time TCY [µs] 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.04167 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 6.0 5.5 Supply voltage VDD [V] TCY vs VDD (LS (low-speed main) mode) Cycle time TCY [µs] 10 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) TCY vs VDD (LV (low-voltage main) mode) Cycle time TCY [µs] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.25 0.1 0.01 0 1.0 2.0 1.6 1.8 3.0 4.0 5.0 5.5 6.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) TI/TO Timing t TIH t TIL TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing t INTH t INTL INTP0 to INTP7 Key Interrupt Input Timing t KR KR0 to KR3 RESET Input Timing t RSL RESET R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 30.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Transfer rate Symbol Note 1 Conditions 2.4 V ≤ EVDD = VDD ≤ 5.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) UART mode connection diagram (during communication at same potential) Rx TxDq User's device RL78 microcontroller RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions 2.7 V ≤ EVDD ≤ 5.5 V 2.4 V ≤ EVDD ≤ 5.5 V HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. MIN. MIN. MAX. MAX.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) (3) During communication at same potential (CSI mode) (slave mode, SCKp...
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol HS Conditions LS (low- LV (low- (high- speed voltage speed main) main) main) Mode Mode Unit Para Symbol Conditions meter Mode Delay time from tKSO2 C = 30 pF Note 4 4.0 V ≤ EVDD ≤ 5.5 V SCKp↓ to SOp output Note 3 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 SIp microcontroller SO User's device SOp SI CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Transfer rate Reception 4.0 V ≤ EVDD ≤ 5.5 V, MAX. MIN. MAX. fMCK/6 Note 1 Note 1 4.0 1.3 0.6 Mbps fMCK/6 fMCK/6 fMCK/6 bps Note 1 Note 1 4.0 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) Mode main) Mode MIN. Transfer rate Transmission 4.0 V ≤ EVDD ≤ 5.5 V, MAX. Note 1 MIN. LV (low-voltage Unit main) Mode MAX. MIN. Note 1 MAX. Note 1 bps Mbps 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V 1 Maximum transfer rate = {−Cb × Rb × ln (1 − Baud rate error (theoretical value) = 2.0 )} × 3 Vb [bps] 1 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (5) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- speed main) main) Mode voltage main) Mode MIN. SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD ≤ 5.5 V, MAX. Mode MIN. MAX. MIN.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- speed main) main) Mode voltage main) Mode MIN. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD ≤ 5.5 V, MAX. Unit Mode MIN. MAX. MIN. MAX.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low- LV (low- Unit speed main) speed main) voltage main) Mode Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp setup time Note 1 (to SCKp↑) tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low- LV (low- Unit speed main) speed main) voltage main) Mode Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp hold time Note 2 (from SCKp↓) tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode connection diagram (during communication at different potential) Vb Rb SCKp SIp RL78 microcontroller SOp Vb Rb SCK SO User's device SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY1 t KL1 t KH1 SCKp t SIK1 SIp t KSI1 Input data t KSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions (1/2) HS (high- LS (low-speed LV (low- speed main) main) mode voltage main) mode MIN. SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V MAX.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions (2/2) HS (high- LS (low-speed LV (low- speed main) main) mode voltage main) mode MIN. Delay time from SCKp↓ Note 5 to SOp output tKSO2 MAX. Unit mode MIN. MAX. MIN. MAX. 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY2 t KL 2 t KH 2 SCKp t SIK2 SIp t KSI2 Input data t KSO 2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.5.2 Serial interface IICA 2 (1) I C standard mode (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- speed main) main) Mode voltage main) Mode SCLA0 clock frequency fSCL Standard mode: fCLK ≥ 1 MHz Mode MIN. MAX. MIN. MIN. MAX. MIN. 2.7 V ≤ EVDD ≤ 5.5 V 0 100 0 100 0 100 2.4 V ≤ EVDD ≤ 5.
RL78/L12 Notes 1. 2. Remark CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2 (2) I C fast mode (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- speed main) main) Mode voltage main) Mode SCLA0 clock frequency fSCL Setup time of restart condition tSU:STA MIN. MAX. MIN. MIN. MAX. MIN. 2.7 V ≤ EVDD ≤ 5.5 V 0 400 0 400 0 400 fCLK ≥ 3.5 2.4 V ≤ EVDD ≤ 5.5 V 0 400 0 400 0 400 0 400 0 400 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2 (3) I C fast mode plus (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions Fast mode plus: 2.7 V ≤ EVDD ≤ 5.5 V fCLK ≥ 10 MHz HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. MAX. 0 1000 MIN. MAX. MIN. Unit MAX. ⎯ ⎯ kHz 0.26 ⎯ ⎯ μs 2.7 V ≤ EVDD ≤ 5.5 V 0.26 ⎯ ⎯ μs tLOW 2.7 V ≤ EVDD ≤ 5.5 V 0.5 ⎯ ⎯ μs tHIGH 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.6 Analog Characteristics 30.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Reference voltage (−) = AVREFM Reference voltage (−) = VSS Reference voltage (−) = AVREFM ANI0, ANI1 − Refer to 30.6.1 (3). Refer to 30.6.1 (4). ANI16 to ANI23 Refer to 30.6.1 (2).
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI23 (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL MIN. TYP.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23 (TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. TYP.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.6.3 POR circuit characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Detection voltage Minimum pulse width Note Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time 1.46 1.50 1.54 V TPW μs 300 Note Minimum time required for a POR reset when VDD exceeds below VPDR.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.6.4 LVD circuit characteristics (TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Detection Supply voltage level Symbol VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 VLVD13 Minimum pulse width tLW Detection delay time tLD R01UH0330EJ0200 Rev.2.00 Dec 13, 2013 Conditions MIN. TYP. MAX. Unit Power supply rise time 3.98 4.06 4.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.7 LCD Characteristics 30.7.1 Resistance division method (1) Static display mode (TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.0 MAX. Unit VDD V MAX. Unit VDD V MAX. Unit VDD V (2) 1/2 bias method, 1/4 bias method (TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.7.2 Internal voltage boosting method (1) 1/3 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions Note 1 C1 to C4 = 0.47 μF MIN. TYP. MAX. Unit VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) 1/4 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Note 4 Conditions Note 1 C1 to C5 = 0.47 μF MIN. TYP. MAX. Unit VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.7.3 Capacitor split method 1/3 bias method (TA = −40 to +85°C, 2.2 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 C1 to C4 = 0.47 μ F VL2 voltage VL2 C1 to C4 = 0.47 μ F 2/3 VL4 − 0.1 2/3 VL4 2/3 VL4 + 0.1 V VL1 voltage VL1 C1 to C4 = 0.47 μ F 1/3 VL4 − 0.1 1/3 VL4 1/3 VL4 + 0.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Data retention supply voltage Symbol Conditions MIN. TYP. Note VDDDR 1.46 MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 30.11 Timing Specifications for Switching Flash Memory Programming Modes (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Time to complete the tSUINIT Conditions MIN. TYP. POR and LVD reset must be released before MAX. Unit 100 ms the external reset is released.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to +105°C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) There are following differences between the products "G: Industrial applications (TA = -40 to +105°C)" and the products “A: Consumer applications, and G: Industrial applications (TA = -40 to +85°C)”.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbols (1/3) Conditions Unit VDD VDD = EVDD −0.5 to +6.5 V EVDD VDD = EVDD −0.5 to +6.5 V −0.5 to +0.3 V EVSS REGC pin input voltage Ratings VIREGC REGC −0.3 to +2.8 V Note 1 and −0.3 to VDD + 0.3 Input voltage VI1 P10 to P17, P30 to P32, P40 to P43, P50 to P54, P70 to P74, P120, P125 to P127, P140 −0.3 to EVDD + 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Absolute Maximum Ratings (TA = 25°C) Parameter LCD voltage (2/3) Symbols VL1 Conditions VL1 voltage Note 1 Ratings Unit −0.3 to +2.8 V and −0.3 to VL4 + 0.3 VL2 VL3 VL4 VLCAP VLOUT VL2 voltage Note 1 −0.3 to VL4 + 0.3 Note 2 V VL3 voltage Note 1 −0.3 to VL4 + 0.3 Note 2 V VL4 voltage Note 1 CAPL, CAPH voltage COM0 to COM7, External resistance division V −0.3 to VL4 + 0.3 Note 2 V −0.3 to VDD + 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Absolute Maximum Ratings (TA = 25°C) Parameter Output current, high Symbols IOH1 (3/3) Conditions Per pin P10 to P17, P30 to P32, P40 to P43, Ratings Unit −40 mA −70 mA −100 mA P50 to P54, P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of all pins P10 to P14, P40 to P43, P120, −170 mA P130, P140 to P147 P15 to P17, P30 to P32, P50 to P54, P70 to P74, P125 to P127 IOH2 Per pin P20, P21 Total of all pins Outp
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.2 Oscillator Characteristics 31.2.1 X1, XT1 oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Resonator Conditions MIN. Ceramic resonator/ 2.7 V ≤ VDD ≤ 5.5 V 1.0 frequency (fX) crystal resonator 2.4 V ≤ VDD < 2.7 V 1.0 XT1 clock oscillation Crystal resonator X1 clock oscillation Note 32 TYP. MAX. Unit 20.0 MHz 16.0 MHz 35 kHz 32.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.2.2 On-chip oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions fIH MIN. TYP. MAX. Unit 1 24 MHz Notes 1, 2 High-speed on-chip oscillator −20 to +85°C 2.4 V ≤ VDD ≤ 5.5 V −1 +1 % clock frequency accuracy −40 to −20°C 2.4 V ≤ VDD ≤ 5.5 V −1.5 +1.5 % +85 to +105°C 2.4 V ≤ VDD ≤ 5.5 V −2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.3 DC Characteristics 31.3.1 Pin characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol IOH1 Output current, Note 1 high Conditions TYP. MAX. -3.0 Note 2 Unit mA 4.0 V ≤ EVDD ≤ 5.5 V -30.0 mA 2.7 V ≤ EVDD < 4.0 V −8.0 mA 2.4 V ≤ EVDD < 2.7 V −4.0 mA 4.0 V ≤ EVDD ≤ 5.5 V -30.0 mA 2.7 V ≤ EVDD < 4.0 V −15.0 mA 2.4 V ≤ EVDD < 2.7 V −8.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions TYP. MAX. Note 2 8.5 Per pin for P60, P61 15.0 Note 2 Unit mA mA Total of P10 to P14, P40 to P43, P120, 4.0 V ≤ EVDD ≤ 5.5 V P130, P140 to P147 2.7 V ≤ EVDD < 4.0 V Note 3 (When duty = 70% ) 2.4 V ≤ EVDD < 2.7 V 40.0 mA 15.0 mA 9.0 mA 4.0 V ≤ EVDD ≤ 5.5 V 40.0 mA 2.7 V ≤ EVDD < 4.0 V 35.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Input voltage, Symbol VIH1 Conditions P10 to P17, P30 to P32, P40 to P43, (3/5) MIN. Normal input buffer TYP. MAX. Unit 0.8EVDD EVDD V 2.2 EVDD V 2.0 EVDD V 1.50 EVDD V P50 to P54, P70 to P74, P120, high P125 to P127, P140 to P147 VIH2 P10, P11, P15, P16 TTL input buffer 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 3.3 V ≤ EVDD < 4.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output voltage, VOH1 high Conditions MIN. P10 to P17, P30 to P32, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V, P50 to P54, P70 to P74, P120, IOH1 = −3.0 mA P125 to P127, P130, P140 to P147 2.7 V ≤ EVDD ≤ 5.5 V, IOH1 = −2.0 mA 2.4 V ≤ EVDD ≤ 5.5 V, IOH1 = −1.5 mA VOH2 P20, P21 (4/5) 2.4 V ≤ VDD ≤ 5.5 V, TYP. MAX. EVDD − Unit V 0.7 EVDD − V 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Input leakage Symbol ILIH1 Conditions P10 to P17, P30 to P32, (5/5) MIN. TYP. MAX.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.3.2 Supply current characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Supply current Symbol IDD1 Conditions Operating mode Note 1 HS (highspeed main) Note 5 mode fIH = 24 MHz fIH = 16 MHz HS (highspeed main) Note 5 mode MIN. Note 3 Note 3 fMX = 20 MHz Note 2 , VDD = 5.0 V fMX = 20 MHz Note 2 , VDD = 3.0 V fMX = 10 MHz MAX. Basic operation VDD = 5.0 V 1.5 VDD = 3.0 V 1.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions Supply IDD2 HALT current Note 2 mode Note 1 HS (highspeed main) Note 7 mode HS (highspeed main) Note 7 mode fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 fMX = 20 MHz MIN. Note 3 , VDD = 5.0 V fMX = 20 MHz Note 3 , VDD = 3.0 V fMX = 10 MHz Note 3 , VDD = 5.0 V fMX = 10 MHz Note 3 , VDD = 3.0 V Note 5 0.44 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Low-speed on- Symbol IFIL Conditions (3/3) MIN. Note 1 TYP. MAX. Unit 0.20 μA 0.08 μA 0.08 μA 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.4 AC Characteristics 31.4.1 Basic operation (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) operation MIN. TYP. HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167 main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 Subsystem clock (fSUB) 2.4 V ≤ VDD ≤ 5.5 V 28.5 30.5 MAX. Unit 1 μs 1 μs 31.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) Cycle time TCY [µs] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.0417 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) TI/TO Timing t TIL t TIH TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing t INTL t INTH INTP0 to INTP7 Key Interrupt Input Timing t KR KR0 to KR3 RESET Input Timing t RSL RESET R01UH0330EJ0200 Rev.2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 31.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Note 1 Unit MAX. fMCK/12 bps 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 5.5 V 2.4 V ≤ EVDD ≤ 5.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 5 tKCY2 4.0 V ≤ EVDD ≤ 5.5 V 2.7 V ≤ EVDD < 4.0 V Unit MAX.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY1, 2 t KL1, 2 t KH1, 2 SCKp t SIK1, 2 SIp t KSI1, 2 Input data t KSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Reception 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V MAX. fMCK/12 Theoretical value of the Unit Note 1 2.0 bps Mbps maximum transfer rate fMCK = fCLK Note 2 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. MAX. Transmission 4.0 V ≤ EVDD ≤ 5.5 V, Transfer rate 2.7 V ≤ Vb ≤ 4.0 V Unit Note 1 Theoretical value of the 2.0 Note 2 bps Mbps maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ EVDD < 4.0 V, 2.
RL78/L12 5. CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V 1 Maximum transfer rate = {−Cb × Rb × ln (1 − Baud rate error (theoretical value) = 1.5 )} × 3 Vb [bps] 1 1.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0, 1), g: PIM and POM number (g = 1) 3.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Unit MAX.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time Note 1 (to SCKp↑) tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Unit MAX. 162 ns 354 ns 958 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 kΩ 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY1 t KL1 t KH1 SCKp t SIK1 SIp t KSI1 Input data t KSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 1 SCKp high-/low-level width tKCY2 Unit MAX. 4.0 V ≤ EVDD ≤ 5.5 V, 20 MHz < fMCK ≤ 24 MHz 24/fMCK ns 2.7 V ≤ Vb ≤ 4.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY2 t KL 2 t KH 2 SCKp t SIK2 SIp t KSI2 Input data t KSO 2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.5.2 Serial interface IICA 2 (1) I C standard mode (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol SCLA0 clock frequency fSCL Setup time of restart condition Hold time Note 1 tHD:STA Hold time when SCLA0 = “L” tLOW Hold time when SCLA0 = “H” tHIGH Data setup time (reception) tSU:DAT Note 2 Data hold time (transmission) Setup time of stop condition Bus-free time Notes 1. 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 2 (2) I C fast mode (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter SCLA0 clock frequency Setup time of restart Symbol fSCL tSU:STA condition Hold time Note 1 tHD:STA Hold time when SCLA0 tLOW = “L” Hold time when SCLA0 tHIGH = “H” Data setup time tSU:DAT (reception) Data hold time tHD:DAT Note 2 (transmission) Setup time of stop tSU:STO condition Bus-free time Notes 1. 2.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.6 Analog Characteristics 31.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Reference voltage (−) = AVREFM Reference voltage (−) = VSS Reference voltage (−) = AVREFM ANI0, ANI1 − Refer to 31.6.1 (3). Refer to 31.6.1 (4). ANI16 to ANI23 Refer to 31.6.1 (2).
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI23 (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Resolution Conditions MIN. RES Note 1 TYP. 8 MAX. Unit 10 bit ±7.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23 (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the TYP. MAX. 1.05 1.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.6.4 LVD circuit characteristics (TA = −40 to +105°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Detection Supply voltage level Symbol VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Conditions MIN. TYP. MAX. Unit Power supply rise time 3.90 4.06 4.22 V Power supply fall time 3.83 3.98 4.13 V Power supply rise time 3.60 3.75 3.90 V Power supply fall time 3.53 3.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.6.5 Power supply voltage rising slope characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Power supply voltage rising slope Caution Conditions MIN. TYP. MAX. Unit 54 V/ms SVDD Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 31.4 AC Characteristics. 31.7 LCD Characteristics 31.7.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.7.2 Internal voltage boosting method (1) 1/3 bias method (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions Note 1 C1 to C4 = 0.47 μF MIN. TYP. MAX. Unit VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) 1/4 bias method (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Note 4 Conditions Note 1 C1 to C5 = 0.47 μF MIN. TYP. MAX. Unit VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.7.3 Capacitor split method 1/3 bias method (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 C1 to C4 = 0.47 μ F VL2 voltage VL2 C1 to C4 = 0.47 μ F 2/3 VL4 − 0.1 2/3 VL4 2/3 VL4 + 0.1 V VL1 voltage VL1 C1 to C4 = 0.47 μ F 1/3 VL4 − 0.1 1/3 VL4 1/3 VL4 + 0.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.9 Flash Memory Programming Characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions System clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V Number of code flash rewrites Cerwr Retained for 20 years TA = 85°C MIN. TYP. 1 1,000 MAX.
RL78/L12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 31.11 Timing Specifications for Switching Flash Memory Programming Modes (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. Time to complete the communication tSUINIT POR and LVD reset must be released before for the initial setting after the the external reset is released. TYP. MAX.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS CHAPTER 32 PACKAGE DRAWINGS 32.1 32-pin products R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2 HD 2 D 17 16 24 25 detail of lead end 1 E c HE θ 32 8 1 L 9 e (UNIT:mm) 3 b x M A A2 ITEM D DIMENSIONS 7.00±0.10 E 7.00±0.10 HD 9.00±0.20 HE 9.00±0.20 A 1.70 MAX. A1 0.10±0.10 A2 y A1 1.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS 32.2 44-pin products R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 HD D detail of lead end A3 23 22 33 34 c L E Lp HE L1 (UNIT:mm) 12 11 44 1 ZE e ZD b x M S A A2 S y S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS 32.3 48-pin products R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 HD D detail of lead end 36 25 37 A3 24 c L E Lp HE L1 (UNIT:mm) 13 48 12 1 ZE e ZD b x M S A ITEM D DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS 32.4 52-pin products R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA R5F10RJ8GFA, R5F10RJAGFA, R5F10RJCGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP52-10x10-0.65 PLQP0052JA-A P52GB-65-GBS-1 0.3 HD D 2 27 39 40 detail of lead end 26 c 1 E HE L 52 14 1 13 e (UNIT:mm) 3 b x M A A2 y A1 ITEM D 10.00±0.10 E 10.00±0.10 HD 12.00±0.20 HE 12.00±0.20 A 1.70 MAX. A1 0.10±0.05 A2 1.40 b 0.32±0.05 c 0.145±0.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS 32.5 64-pin products R5F10RLAAFA, R5F10RLCAFA R5F10RLAGFA, R5F10RLCGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51 HD D detail of lead end 48 33 49 32 A3 c L E Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A2 S S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. DIMENSIONS 12.00±0.20 E 12.00±0.20 HD 14.00±0.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS R5F10RLAAFB, R5F10RLCAFB R5F10RLAGFB, R5F10RLCGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 HD D detail of lead end 48 33 49 A3 32 c L E Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S ITEM D DIMENSIONS 10.00±0.20 E 10.00±0.20 HD 12.00±0.20 HE 12.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.
RL78/L12 CHAPTER 32 PACKAGE DRAWINGS R5F10RLAANB, R5F10RLCANB R5F10RLAGNB, R5F10RLCGNB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN64-8x8-0.40 PWQN0064LA-A P64K8-40-9B5-1 0.16 D DETAIL OF A E PART A S A S y S (UNIT:mm) ITEM D2 A 1 EXPOSED DIE PAD 16 64 17 D 8.00 ± 0.05 E 8.00 ± 0.05 A 0.75 ± 0.05 b 0.20 ± 0.05 e 0.40 Lp B DIMENSIONS 0.40 ± 0.10 x 0.05 y 0.
RL78/L12 APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/10) Page Though out Description Classification Renamed operation speed mode control register to subsystem clock supply mode control (b) register (OSMC) CHAPTER 1 OUTLINE p.1 Modification of 1.1 Features (b) p.3 Modification of Figure 1-1 (b) p.4 Modification of part number, note, and caution (b) p.5 to 10 Deletion of COMEXP pin in 1.3.1 to 1.3.5. (b) p.
RL78/L12 APPENDIX A REVISION HISTORY (2/10) Page Description Classification p.121 Addition of 4.5.3 Register setting examples for used port and alternate functions (c) p.129 Modification of description in 4.6.2 Notes on specifying the pin settings (c) CHAPTER 5 CLOCK GENERATOR p.131 Modification of description in 5.1 Functions of Clock Generator (c) p.133 Modification of description in Figure 5-1 (b) p.141 Modification of description in 5.3.
RL78/L12 APPENDIX A REVISION HISTORY (3/10) Page Description Classification p.253 Modification of description in Figure 6-64 (c) p.254 Modification of Figure 6-65 (c) p.258 Modification of description in Figure 6-68 (c) p.260 Modification of Figure 6-69 (c) p.264, 265 Modification of description in Figure 6-73 (c) CHAPTER 7 REAL-TIME CLOCK p.284 Modification of description in 7.1 Functions of Real-time Clock (c) p.285 Modification of description in Figure 7-1 (c) p.
RL78/L12 APPENDIX A REVISION HISTORY (4/10) Page Description Classification CHAPTER 11 A/D CONVERTER p.334 Modification of description in 11.1 Function of A/D Converter (c) p.335 Modification of description in Figure 11-1 (c) p.337 Modification of description in 11.2 Configuration of A/D Converter (c) p.343 Modification of caution 4 in Figure 11-4 (c) p.344 Modification of note 3 and caution 1 in Table 11-3 (1/4) (c) p.
RL78/L12 APPENDIX A REVISION HISTORY (5/10) Page Description Classification p.405 Addition of Figure 12-18 (c) p.407 Addition of 12.3.17 Registers controlling port functions of serial input/output pins (c) Modification of description in 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01) (c) p.410 Communication p.416 Modification of Figure 12-26 (c) p.418 Modification of Figure 12-28 (c) p.420 Modification of Figure 12-30 (c) p.424 Modification of Figure 12-33 (c) p.
RL78/L12 APPENDIX A REVISION HISTORY (6/10) Page Description Classification CHAPTER 13 SERIAL INTERFACE IICA p.522 Modification of caution 1 in Figure 13-5 (c) p.526 Addition of note 2 to Figure 13-6 (3/4) (c) p.527 Addition of note to Figure 13-6 (4/4) (c) p.533 Modification of description in Figure 13-9 (2/2) (c) p.534 Modification of remark in 13.3.7 IICA high-level width setting register 0 (IICWH0) (c) p.559 Modification of Figure 13-28 (c) p.
RL78/L12 APPENDIX A REVISION HISTORY (7/10) Page Description Classification CHAPTER 18 KEY INTERRUPT FUNCTION p.724 Modification of description in Table 18-1 (c) p.725 Modification of description in Table 18-2 (c) CHAPTER 19 STANDBY FUNCTION p.733 Modification of caution in 19.3.1 HALT mode (c) p.736 Modification of note 2 in Figure 19-1 (c) p.737 Modification of Figures 19-2 (1) and (2) (c) p.740 Modification of Figure 19-3 (1), note 2, and remark 1 (c) p.
RL78/L12 APPENDIX A REVISION HISTORY (8/10) Page Description Classification CHAPTER 23 SAFETY FUNCTIONS p.776 Modification of (6), (7), and remark in 23.1 Overview of Safety Functions (c) p.780 Modification of description in Figure 23-3 (c) p.783 Modification of caution and remarks in Figure 23-7 (c) p.784 Addition of Figure 23-8 (c) p.787 Modification of description and note in Figure 23-11 (c) p.789 Modification of description in 23.3.7 Frequency detection function (c) p.
RL78/L12 APPENDIX A REVISION HISTORY (9/10) Page Description Classification p.859 Modification of table, notes 2 and 3 in 30.3.1 Pin characteristics (1/5) (c) p.860 Modification of notes 1 and 3 in 30.3.1 Pin characteristics (2/5) (c) p.865 Modification of notes 1 and 4 in 30.3.2 Supply current characteristics (1/3) (c) p.866, 867 Modification of table, notes 1, 5, and 6 in 30.3.2 Supply current characteristics (2/3) (c) p.868, 869 Modification of table, notes 1, 3, 4, and 5 to 10 in 30.3.
RL78/L12 APPENDIX A REVISION HISTORY (10/10) Page p.902 Description Modification of the table in 30.6.2 Temperature sensor/internal reference voltage Classification (c) characteristics p.903 Modification of the table and note in 30.6.3 POR circuit characteristics (c) p.905 Modification of the table of LVD Detection Voltage of Interrupt & Reset Mode (c) p.905 Modification from VDD rise slope to Power supply voltage rising slope in 30.6.5 Supply (c) voltage rise time p.
RL78/L12 APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/10) Edition Rev.1.
RL78/L12 APPENDIX A REVISION HISTORY (2/10) Edition Rev.1.00 Description Chapter Modification of description in 4.1 Port Functions CHAPTER 4 Addition of caution to 4.3 Registers Controlling Port Function PORT FUNCTIONS Modification of Figure 4-2. Format of Port Register (64-pin products) Modification of description and addition of caution to 4.3.3 Pull-up resistor option registers (PUxx) Addition of description in 4.3.5 Port output mode registers (POM1) Addition of cautions 1 and 2 to Figure 4-6.
RL78/L12 APPENDIX A REVISION HISTORY (3/10) Edition Rev.1.00 Description Chapter Modification of note 1 in Figure 6-12. Format of Timer Mode Register mn (TMRmn) CHAPTER 6 Modification of Setting of starting counting and interrupt and addition of note 3 in Figure 6-12. TIMER ARRAY UNIT Format of Timer Mode Register mn (TMRmn) (4/4) Modification of description in Figure 6-16. Format of Timer Channel Stop register m (TTm) Addition of caution to Figure 6-17.
RL78/L12 APPENDIX A REVISION HISTORY (4/10) Edition Rev.1.00 Description Chapter Modification of description and cautions 1 to 3 and addition of note in Figure 11-7. Format of A/D CHAPTER 11 Converter Mode register 2 (ADM2) (1/2) A/D CONVERTER Modification of caution and addition of note and remark in Figure 11-7. Format of A/D Converter Mode register 2 (ADM2) (2/2) Addition of note to 11.3.5 10-bit A/D conversion result register (ADCR), and 11.3.
RL78/L12 APPENDIX A REVISION HISTORY (5/10) Edition Rev.1.00 Description Chapter Modification of description in 12.5.3 Master transmission/reception CHAPTER 12 Modification of note to 12.5.4 Slave transmission, 12.5.5 Slave reception, 12.5.6 Slave SERIAL ARRAY UNIT transmission/reception Modification of description in 12.5.7 SNOOZE mode function Modification of caution in Figures 12-70 and 12-72 Modification of description in 12.6.1 UART transmission and 12.6.
RL78/L12 APPENDIX A REVISION HISTORY (6/10) Edition Description Rev.1.00 Modification of cautions 1, 3 in Figure 14-5. Format of Operation Speed Mode Control Register CHAPTER 14 (OSMC) LCD Modification of description and cautions 2, 4 in Figure 14-6. Format of LCD Clock Control CONTROLLER/DRIVER Chapter Register 0 (LCDC0) (1/2) Modification of description and cautions 2, 3 in Figure 14-6. Format of LCD Clock Control Register 0 (LCDC0) (2/2) Modification of Table 14-5.
RL78/L12 APPENDIX A REVISION HISTORY (7/10) Edition Rev.1.00 Description Chapter Addition of description CHAPTER 17 Deletion of caution 2 in Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, INTERRUPT IF1L, IF1H, IF2L) (64-pin) FUNCTION Modification of Figure 17-8. Interrupt Request Acknowledgment Timing (Minimum Time) and Figure 17-9. Interrupt Request Acknowledgment Timing (Maximum Time) Modification of Table 17-5.
RL78/L12 APPENDIX A REVISION HISTORY (8/10) Edition Rev.1.00 Description Chapter Modification of Figure 22-1. Block Diagram of Voltage Detector CHAPTER 22 Modification of notes 1, 3 in Figure 22-2. Format of Voltage Detection Register (LVIM) VOLTAGE Addition of Table 22-1. LVD Operation Mode and Detection Voltage Settings for User Option DETECTOR Byte (000C1H) Modification of 22.4.1 When used as reset mode Modification of 22.4.2 When used as interrupt mode Modification of description in 22.4.
RL78/L12 APPENDIX A REVISION HISTORY (9/10) Edition Rev.1.00 Description Modification of error in Table 29-5. Operation List (10/17) Chapter CHAPTER 29 INSTRUCTION SET Addition of cautions 2, 3 to CHAPTER 30 ELECTRICAL SPECIFICATIONS (deletion of Pins CHAPTER 30 Mounted According to Product) ELECTRICAL Addition of description, note 3, and remark 2 to 30.1 Absolute Maximum Ratings SPECIFICATIONS Modification of description and addition of note to 30.1 Absolute Maximum Ratings Modification of 30.
RL78/L12 APPENDIX A REVISION HISTORY (10/10) Edition Ver.0.03 Description Chapter Modification of caution 2 in 1.3.5 64-pin products CHAPTER 1 Modification of I/O port in 1.6 Outline of Functions OUTLINE Modification of Function in 2.1.5 64-pin products CHAPTER 2 Modification of description in 2.2 Description of Pin Functions PIN FUNCTIONS Modification of 2.2.6 (1) Port mode Modification of Table 2-3. Connection of Unused Pins (64-pin products) Modification of Figure 2-1.
RL78/L12 User’s Manual: Hardware Publication Date: Rev.2.
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