Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 948
Dec 13, 2013
31.5.2 Serial interface IICA
(1) I
2
C standard mode
(T
A = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCLA0 clock frequency fSCL
Standard mode:
f
CLK ≥ 1 MHz
2.7 V ≤ EV
DD ≤ 5.5 V 0 100 kHz
2.4 V ≤ EVDD ≤ 5.5 V 0 100 kHz
Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.7 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.7 μ s
Hold time
Note 1
tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.0 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.0 μ s
Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 4.7 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.7 μ s
Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 4.0 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.0 μ s
Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 250 ns
2.4 V ≤ EVDD ≤ 5.5 V 250 ns
Data hold time (transmission)
Note 2
tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 3.45 μ s
2.4 V ≤ EVDD ≤ 5.5 V 0 3.45 μ s
Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 4.0 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.0 μ s
Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 4.7 μ s
2.4 V ≤ EVDD ≤ 5.5 V 4.7 μ s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
HD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: C
b = 400 pF, Rb = 2.7 kΩ