Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 937
Dec 13, 2013
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rate Reception 4.0 V ≤ EVDD ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
f
MCK/12
Note 1
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 2
2.0 Mbps
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
f
MCK/12
Note 1
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 2
2.0 Mbps
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
f
MCK/12
Note 1
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 2
2.0 Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (f
CLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ V
DD ≤ 5.5 V)
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V
DD tolerance (32- to 52-pin
products)/EV
DD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remarks 1. V
b[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 1)
3. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)