Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 935
Dec 13, 2013
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time
Note 5
tKCY2 4.0 V ≤ EVDD ≤ 5.5 V 20 MHz < fMCK 16/fMCK ns
fMCK ≤ 20 MHz 12/fMCK ns
2.7 V ≤ EVDD < 4.0 V 16 MHz < fMCK 16/fMCK ns
fMCK ≤ 16 MHz 12/fMCK ns
2.4 V ≤ EVDD ≤ 5.5 V 12/fMCK and 1000 ns
SCKp high-/low-level
width
tKH2,
t
KL2
4.0 V ≤ EV
DD ≤ 5.5 V tKCY2/2 − 14 ns
2.7 V ≤ EVDD < 4.0 V tKCY2/2 − 16 ns
2.4 V ≤ EVDD < 2.7 V tKCY2/2 − 36 ns
SIp setup time
(to SCKp↑)
Note 1
t
SIK2 2.7 V ≤ EVDD ≤ 5.5 V 1/fMCK + 40 ns
2.4 V ≤ EVDD < 2.7 V 1/fMCK + 60 ns
SIp hold time
(from SCKp↑)
Note 2
t
KSI2 2.4 V ≤ EVDD ≤ 5.5 V 1/fMCK + 62 ns
Delay time from SCKp↓
to SOp output
Note 3
t
KSO2 C = 30 pF
Note 4
4.0 V ≤ EVDD ≤ 5.5 V 2/fMCK + 66 ns
2.7 V ≤ EVDD < 4.0 V 2/fMCK + 66 ns
2.4 V ≤ EVDD < 2.7 V 2/fMCK + 113 Ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM number (g = 1)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
CSI mode connection diagram (during communication at same potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User's device
SIp SO