Datasheet

RL78/L12
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
R01UH0330EJ0200 Rev.2.00 934
Dec 13, 2013
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Notes 1. Set a cycle of 4/f
MCK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 5.5 V 334
Note 1
ns
2.4 V ≤ EVDD ≤ 5.5 V 500
Note 1
ns
SCKp high-/low-level width
t
KH1,
t
KL1
4.0 V ≤ EV
DD ≤ 5.5 V tKCY1/2 − 24 ns
2.7 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 36 ns
2.4 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 76 ns
SIp setup time (to SCKp↑)
Note 2
tSIK1 2.7 V ≤ EVDD ≤ 5.5 V 66 ns
2.4 V ≤ EVDD ≤ 5.5 V 113 ns
SIp hold time (from SCKp↑)
Note 3
tKSI1 2.4 V ≤ EVDD ≤ 5.5 V 38 ns
Delay time from SCKp↓ to
SOp output
Note 4
t
KSO1 C = 30 pF
Note 5
2.4 V ≤ EV
DD ≤ 5.5
V
50 ns