Datasheet

RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 887
Dec 13, 2013
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions
HS (high-
speed main)
Mode
LS (low-
speed main)
Mode
LV (low-
voltage main)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↑)
Note 1
t
SIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
81 479 479 ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
177 479 479 ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
479 479 479 ns
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 3
,
C
b = 30 pF, Rb = 5.5 kΩ
479 479 ns
SIp hold time
(from SCKp↑)
Note 1
t
KSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
19 19 19 ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
19 19 19 ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
19 19 19 ns
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 3
,
C
b = 30 pF, Rb = 5.5 kΩ
19 19 ns
Delay time from SCKp↓ to
SOp output
Note 1
t
KSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
100 100 100 ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
195 195 195 ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
483 483 483 ns
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 3
,
C
b = 30 pF, Rb = 5.5 kΩ
483 483 ns
SIp setup time
(to SCKp↓)
Note 2
t
SIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
44 110 110 ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
44 110 110 ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
110 110 110 ns
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 3
,
C
b = 30 pF, Rb = 5.5 kΩ
110 110 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. Use it with EV
DD ≥ Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance (32-pin to 52-
pin products)/EV
DD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
<R>
<R>
<R>
<R>