Datasheet

RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 886
Dec 13, 2013
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions
HS (high-
speed main)
Mode
LS (low-speed
main) Mode
LV (low-
voltage main)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK
4.0 V ≤ EV
DD ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
300 1150 1150 ns
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
500 1150 1150 ns
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
1150 1150 1150 ns
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note
,
C
b = 30 pF, Rb = 5.5 kΩ
1150 1150 ns
SCKp high-level width tKH1
4.0 V ≤ EV
DD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
t
KCY1/2
− 75
t
KCY1/2
− 75
t
KCY1/2
− 75
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
t
KCY1/2
− 170
t
KCY1/2
− 170
t
KCY1/2
− 170
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
t
KCY1/2
− 458
tKCY1/2
− 458
tKCY1/2
− 458
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note
,
C
b = 30 pF, Rb = 5.5 kΩ
t
KCY1/2
− 458
t
KCY1/2
− 458
ns
SCKp low-level width tKL1
4.0 V ≤ EV
DD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
t
KCY1/2
− 12
t
KCY1/2
− 50
t
KCY1/2
− 50
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
t
KCY1/2
− 18
tKCY1/2
− 50
tKCY1/2
− 50
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
t
KCY1/2
− 50
t
KCY1/2
− 50
t
KCY1/2
− 50
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note
,
C
b = 30 pF, Rb = 5.5 kΩ
t
KCY1/2
− 50
t
KCY1/2
− 50
ns
Note Use it with EVDD ≥ Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance (32-pin to 52-
pin products)/EV
DD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC
characteristics with TTL input buffer selected.
<R>
<R>