Datasheet

RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 877
Dec 13, 2013
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (1/2)
(T
A = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time
Note 5
t
KCY2 4.0 V ≤ EVDD ≤ 5.5 V 20 MHz < fMCK 8/fMCK ns
fMCK ≤ 20 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.7 V ≤ EVDD < 4.0 V 16 MHz < fMCK 8/fMCK ns
fMCK ≤ 16 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.4 V ≤ EVDD ≤ 5.5 V
6/f
MCK
and
500
6/f
MCK 6/fMCK ns
1.8 V ≤ EVDD < 2.4 V 6/fMCK 6/fMCK ns
1.6 V ≤ EVDD < 1.8 V 6/fMCK ns
SCKp high-/low-
level width
tKH2,
t
KL2
4.0 V ≤ EV
DD ≤ 5.5 V
t
KCY2/2
− 7
t
KCY2/2
− 7
t
KCY2/2
− 7
ns
2.7 V ≤ EVDD < 4.0 V
t
KCY2/2
− 8
tKCY2/2
− 8
tKCY2/2
− 8
ns
2.4 V ≤ EVDD < 2.7 V
t
KCY2/2
− 18
t
KCY2/2
− 18
t
KCY2/2
− 18
ns
1.8 V ≤ EVDD < 2.4 V
t
KCY2/2
− 18
t
KCY2/2
− 18
ns
1.6 V ≤ EVDD < 1.8 V
t
KCY2/2
− 66
ns
SIp setup time
(to SCKp↑)
Note 1
t
SIK2 2.7 V ≤ EVDD ≤ 5.5 V
1/f
MCK
+ 20
1/f
MCK
+ 30
1/f
MCK
+ 30
ns
2.4 V ≤ EVDD < 2.7 V
1/f
MCK
+ 30
1/f
MCK
+ 30
1/f
MCK
+ 30
1.8 V ≤ EVDD < 2.4 V
1/f
MCK
+ 30
1/f
MCK
+ 30
ns
1.6 V ≤ EVDD < 1.8 V
1/f
MCK
+ 40
ns
SIp hold time
(from SCKp↑)
Note 2
t
KSI2 2.4 V ≤ EVDD ≤ 5.5 V
1/f
MCK
+ 31
1/f
MCK
+ 31
1/f
MCK
+ 31
ns
1.8 V ≤ EVDD < 2.4 V
1/f
MCK
+ 31
1/f
MCK
+ 31
ns
1.6 V ≤ EVDD < 1.8 V
1/f
MCK
+
250
ns
(Notes, Caution, and Remarks are listed on the next page.)
<R>
<R>