Datasheet
RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 876
Dec 13, 2013
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Notes 1. For CSI00, set a cycle of 2/f
MCK or longer. For CSI01, set a cycle of 4/fMCK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
(Remarks are listed on the next page.)
Parameter Symbol Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 5.5 V 167
Note 1
500
Note 1
1000
Note 1
ns
2.4 V ≤ EVDD ≤ 5.5 V 250
Note 1
500
Note 1
1000
Note 1
ns
1.8 V ≤ EVDD ≤ 5.5 V 500
Note 1
1000
Note 1
ns
1.6 V ≤ EVDD ≤ 5.5 V 1000
Note 1
ns
SCKp high-/low-level width
t
KH1,
t
KL1
4.0 V ≤ EV
DD ≤ 5.5 V
t
KCY1/2
− 12
tKCY1/2
− 50
tKCY1/2
− 50
ns
2.7 V ≤ EVDD ≤ 5.5 V
t
KCY1/2
− 18
t
KCY1/2
− 50
t
KCY1/2
− 50
ns
2.4 V ≤ EVDD ≤ 5.5 V
t
KCY1/2
− 38
t
KCY1/2
− 50
t
KCY1/2
− 50
ns
1.8 V ≤ EVDD ≤ 5.5 V
t
KCY1/2
− 50
tKCY1/2
− 50
ns
1.6 V ≤ EVDD ≤ 5.5 V
t
KCY1/2
− 100
ns
SIp setup time (to SCKp↑)
Note 2
t
SIK1 2.7 V ≤ EVDD ≤ 5.5 V 44 110 110 ns
2.4 V ≤ EVDD ≤ 5.5 V 75 110 110 ns
1.8 V ≤ EVDD ≤ 5.5 V 110 110 ns
1.6 V ≤ EVDD ≤ 5.5 V 220 ns
SIp hold time (from SCKp↑)
Note 3
t
KSI1 2.4 V ≤ EVDD ≤ 5.5 V 19 19 19 ns
1.8 V ≤ EVDD ≤ 5.5 V 19 19
1.6 V ≤ EVDD ≤ 5.5 V 19
Delay time from SCKp↓ to
SOp output
Note 4
t
KSO1
C = 30 pF
Note 5
2.4 V ≤ EV
DD ≤ 5.5 V 25 25 25 ns
1.8 V ≤ EVDD ≤ 5.5 V 25 25
1.6 V ≤ EVDD ≤ 5.5 V 25
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