Datasheet

RL78/L12 CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
R01UH0330EJ0200 Rev.2.00 874
Dec 13, 2013
30.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIL/VOL
Test points
V
IH/VOH
VIL/VOL
30.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(T
A = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
Note 1
2.4 V ≤ EVDD = VDD ≤ 5.5 V fMCK/6 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 2
4.0 1.3 0.6 Mbps
1.8 V ≤ EVDD = VDD ≤ 5.5 V fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 2
1.3 0.6 Mbps
1.6 V ≤ EVDD = VDD ≤ 5.5 V fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 2
0.6 Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (f
CLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ V
DD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ V
DD ≤ 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V ≤ V
DD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
<R>
<R>
<R>
<R>