Datasheet

RL78/L12 CHAPTER 3 CPU ARCHITECTURE
R01UH0330EJ0200 Rev.2.00 59
Dec 13, 2013
Table 3-3. Vector Table (2/2)
Vector Table Address Interrupt Source
64-pin 52-pin 48-pin 44-pin 32-pin
0030H INTRTC
√ √ √ √ √
0032H INTIT
√ √ √ √ √
0034H INTKR
√ √ √ √ √
003CH INTTM04
√ √ √ √ √
003EH INTTM05
√ √ √ √ √
0040H INTTM06
√ √ √ √ √
0042H INTTM07
√ √ √ √ √
0044H INTLCD0
√ √ √ √ √
0046H INTP6
√ − − − −
0048H INTP7
√ − − − −
004AH INTMD
√ √ √ √ √
004CH INTFL
√ √ √ √ √
007EH BRK
√ √ √ √ √
Remark √: Mounted
−: Not mounted
(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set
the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. For details, see CHAPTER 25 OPTION
BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH can be used as an on-chip debug security ID setting area. For details, see
CHAPTER 27 ON-CHIP DEBUG FUNCTION.