Datasheet

RL78/L12 CHAPTER 3 CPU ARCHITECTURE
R01UH0330EJ0200 Rev.2.00 58
Dec 13, 2013
Table 3-3. Vector Table (1/2)
Vector Table Address Interrupt Source
64-pin 52-pin 48-pin 44-pin 32-pin
0000H
RESET, POR, LVD, WDT,
TRAP, IAW, RPE
√ √ √ √ √
0004H INTWDTI
√ √ √ √ √
0006H INTLVI
√ √ √ √ √
0008H INTP0
√ √ √ √ √
000AH INTP1
√ √ √ √ √
000CH INTP2
√ √ √ √ √
000EH INTP3
√ √ √ √ −
0010H INTP4
√ √ √ √ −
0012H INTP5
√ √ √ − −
0014H INTDMA0
√ √ √ √ √
0016H INTDMA1
√ √ √ √ √
0018H INTST0
√ √ √ √ √
INTCSI00
√ √ √ √ √
001AH INTSR0
√ √ √ √ √
INTCSI01
√ √ √ √ √
001CH INTSRE0
√ √ √ √ √
INTTM01H
√ √ √ √ √
0020H INTTM00
√ √ √ √ √
0024H INTTM03H
√ √ √ √ √
0026H INTIICA0
√ √ √ √ √
0028H INTTM01
√ √ √ √ √
002AH INTTM02
√ √ √ √ √
002CH INTTM03
√ √ √ √ √
002EH INTAD
√ √ √ √ √
Remark √: Mounted
−: Not mounted