Datasheet

RL78/L12 CHAPTER 20 RESET FUNCTION
R01UH0330EJ0200 Rev.2.00 750
Dec 13, 2013
Note P40 and P130 become the following state.
• P40: High-impedance during the external reset period or reset period by the POR. High level during other
types of reset (connected to the internal pull-up resistor).
• P130: Low level during the reset period
Remark f
IH: High-speed on-chip oscillator clock
fX: X1 oscillation clock
f
EX: External main system clock
f
XT: XT1 oscillation clock
fEXS: External subsystem clock
f
IL: Low-speed on-chip oscillator clock
Table 20-2. State of Hardware After Receiving a Reset Signal
Hardware After Reset
Acknowledgment
Note
Program counter (PC) The contents of the
reset vector table
(0000H, 0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 06H
RAM Data memory Undefined
General-purpose registers Undefined
Note During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark For the state of the special function register (SFR) after receiving a reset signal, see 3.2.4 Special function
registers (SFRs) and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function
Registers).
<R>
<R>
<R>