Datasheet

RL78/L12 CHAPTER 19 STANDBY FUNCTION
R01UH0330EJ0200 Rev.2.00 739
Dec 13, 2013
Table 19-2. Operating Statuses in STOP Mode
STOP Mode Setting
Item
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-Speed On-Chip
Oscillator Clock (f
IH)
When CPU Is Operating on
X1 Clock (f
X)
When CPU Is Operating on
External Main System Clock
(f
EX)
System clock Clock supply to the CPU is stopped
Main system clock fIH Stopped
fX
fEX
Subsystem clock fXT Status before STOP mode was set is retained
fEXS
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory Operation stopped
RAM Operation stopped
Port (latch) Status before STOP mode was set is retained
Timer array unit Operation disabled
Real-time clock (RTC) Operable
12-bit interval timer
Watchdog timer See CHAPTER 10 WATCHDOG TIMER
Clock output/buzzer output Operates when the subsystem clock is selected as the clock source for counting and the
RTCLPC bit is 0 (operation is disabled when a clock other than the subsystem clock is selected
and the RTCLPC bit is not 0).
A/D converter Wakeup operation is enabled (switching to the SNOOZE mode)
Serial array unit (SAU)
Wakeup operation is enabled only for CSI00 and UART0 (switching to the SNOOZE mode)
Operation is disabled for anything other than CSI00 and UART0
Serial interface (IICA)
Wakeup by address match operable
LCD driver/controller Operable (However, this depends on the status of the clock selected as the LCD source clock:
operation is possible if the selected clock is operating, but operation will stop if the selected
clock is stopped.)
Multiplier and divider/multiply-
accumulator
Operation disabled
DMA controller
Power-on-reset function Operable
Voltage detection function
External interrupt
Key interrupt function
CRC
operation
function
High-speed CRC
Operation stopped
General-purpose
CRC
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
f
IH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
f
X: X1 clock fEX: External main system clock
f
XT: XT1 clock fEXS: External subsystem clock