Datasheet

RL78/L12 CHAPTER 19 STANDBY FUNCTION
R01UH0330EJ0200 Rev.2.00 737
Dec 13, 2013
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-2. HALT Mode Release by Reset (1/2)
(1) When high-speed on-chip oscillator clock is used as CPU clock
Reset
period
Wait for oscillation accuracy stabilization
Oscillates Oscillates
HALT
instruction
Oscillation
stopped
HALT mode Note
Normal operation
(high-speed
on-chip
oscillator clock)
Normal operation
(high-speed
on-chip
oscillator clock)
Status of CPU
Reset signal
High-speed
on-chip oscillator
clock
(2) When high-speed system clock is used as CPU clock
Oscillates Oscillates
Oscillation stabilization time
(check by using OSTC register)
Normal operation mode
(high-speed on-chip
oscillator clock)
Starting X1 oscillation is
specified by software.
HALT
instruction
Oscillation
stopped
Reset
period
Oscillation
stopped
HALT mode
Normal operation
(high-speed
system clock) Note
Status of CPU
High-speed
system clock
(X1 oscillation)
Reset signal
Note For the reset processing time, see CHAPTER 20 RESET FUNCTION.
For the reset processing time of the power-on-reset circuit (POR) and voltage detector (LVD), see
CHAPTER 21 POWER-ON-RESET CIRCUIT.
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