Datasheet

RL78/L12 CHAPTER 18 KEY INTERRUPT FUNCTION
R01UH0330EJ0200 Rev.2.00 731
Dec 13, 2013
The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 18-9 below. A falling
edge is also input to the KR1 and KR3 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KRF1 bit
is set when the KRF0 bit is cleared. A key interrupt (INTKR) is therefore generated one clock (f
CLK) after the KRF0 bit is
cleared (<1> in the figure). Also, after a falling edge has been input to the KR3 pin, a low level continues to be input to this
pin (<3> in the figure) until the KRF1 bit is cleared (<2> in the figure). A key interrupt (INTKR) is therefore generated one
clock (fCLK) after the KRF1 bit is cleared (<4> in the figure). It is thus possible to generate a key interrupt (INTKR) when
a valid edge is input to multiple channels.
Figure 18-9. Operation of INTKR Signal When Key Interrupts Are Input to Multiple Channels
(When KRMD = 1 and KREG = 0)
<3>
<2>
<1>
Note 1
Note 2 Note 2 Note 2
Delay
time
<4>
KR0
KR1
KR3
KRF0
KRF1
INTKR
KRIF
KRF3
Cleared by software
Cleared by software
Cleared by software
Delay
time
Clear ClearClear
Note 1
Note 1
Delay
time
Notes 1. The maximum delay time is the maximum value of the high-level width and low-level width of the key
interrupt input (see 30.4 or 31.4 AC Characteristics for details).
2. Acknowledgment of vectored interrupt request or bit cleared by software
Remark f
CLK: CPU/peripheral hardware clock frequency