Datasheet

RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0330EJ0200 Rev.2.00 713
Dec 13, 2013
17.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0)
These registers specify the valid edge for INTP0 to INTP7.
The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 17-5. Format of External Interrupt Rising Edge Enable Register (EGP0) and External Interrupt Falling Edge
Enable Register (EGN0) (64-pin products)
Address: FFF38H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0
Address: FFF39H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0
EGPn EGNn INTPn pin valid edge selection (n = 0 to 7)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Table 17-3 shows the ports corresponding to the EGPn and EGNn bits.