Datasheet
RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0330EJ0200 Rev.2.00 711
Dec 13, 2013
17.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H,
PR12L)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, or 2L).
The PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, and PR12L registers can be set by a 1-
bit or 8-bit memory manipulation instruction. If the PR00L and PR00H registers, the PR01L and PR01H registers, the
PR10L and PR10H registers, and the PR11L and PR11H registers are combined to form 16-bit registers PR00, PR01,
PR10, and PR11, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 17-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L,
PR10H, PR11L, PR11H, PR12L) (64-pin products) (1/2)
Address: FFFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0
Address: FFFECH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1
Address: FFFE9H After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
PR00H 1 TMPR000 1
SREPR00
TMPR001H
SRPR00
CSIPR001
STPR00
CSIPR000
DMAPR01 DMAPR00
Address: FFFEDH After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
PR10H
1
TMPR100
1
SREPR10
TMPR101H
SRPR10
CSIPR101
STPR10
CSIPR100
DMAPR11 DMAPR10
Address: FFFEAH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR01L ITPR0 RTCPR0 ADPR0 TMPR003 TMPR002 TMPR001 IICAPR00 TMPR003H
Address: FFFEEH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR11L ITPR1 RTCPR1 ADPR1 TMPR103 TMPR102 TMPR101 IICAPR10 TMPR103H