Datasheet

RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0330EJ0200 Rev.2.00 708
Dec 13, 2013
17.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon
reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, IF1H, and IF2L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When
the IF0L and IF0H registers, the IF1L and IF1H registers are combined to form 16-bit registers IF0 and IF1, they can be
set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L) (64-pin products)
Address: FFFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF
Address: FFFE1H After reset: 00H R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
IF0H 0 TMIF00 0
SREIF0
TMIF01H
SRIF0
CSIIF01
STIF0
CSIIF00
DMAIF1 DMAIF0
Address: FFFE2H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1L ITIF RTCIF ADIF TMIF03 TMIF02 TMIF01 IICAIF0 TMIF03H
Address: FFFE3H After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 <0>
IF1H TMIF07 TMIF06 TMIF05 TMIF04 0 0 0 KRIF
Address: FFFD0H After reset: 00H R/W
Symbol 7 6 5 <4> <3> <2> <1> <0>
IF2L 0 0 0 FLIF MDIF PIF7 PIF6 0
XXIFX Interrupt request flag
0 No interrupt request signal is generated
1 Interrupt request is generated, interrupt request status
(Cautions are listed on the next page)