Datasheet

RL78/L12 CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0330EJ0200 Rev.2.00 700
Dec 13, 2013
Table 17-1. Interrupt Source List (1/3)
Interrupt
Type
Default Priority
Note 1
Interrupt Source
Internal/
External
Vector
Table
Address
Basic Configuration Type
Note 2
64-pin 52-pin 48-pin 44-pin 32-pin
Name Trigger
Maskable 0 INTWDTI Watchdog timer interval
Note 3
(75% of overflow time +1/2fIL)
Internal 0004H (A) √ √ √ √ √
1 INTLVI Voltage detection
Note 4
0006H √ √ √ √ √
2 INTP0 Pin input edge detection External 0008H (B) √ √ √ √ √
3 INTP1 000AH √ √ √ √ √
4 INTP2 000CH √ √ √ √ √
5 INTP3 000EH √ √ √ √ −
6 INTP4 0010H √ √ √ √ −
7 INTP5 0012H √ √ √ − −
8 INTDMA0 End of DMA0 transfer Internal 0014H (A) √ √ √ √ √
9 INTDMA1 End of DMA1 transfer 0016H √ √ √ √ √
10 INTST0 UART0 transmission transfer end
or buffer empty interrupt
0018H √ √ √ √ √
INTCSI00 CSI00 transfer end or buffer
empty interrupt
√ √ √ √ √
11 INTSR0 UART0 reception transfer end 001AH √ √ √ √ √
INTCSI01 CSI01 transfer end or buffer
empty interrupt
√ √ √ √ √
12 INTSRE0 UART0 reception communication
error occurrence
001CH √ √ √ √ √
INTTM01H End of timer channel 01 count or
capture (at higher 8-bit timer
operation)
√ √ √ √ √
13 INTTM00 End of timer channel 00 count or
capture
0020H √ √ √ √ √
14 INTTM03H End of timer channel 03 count or
capture (at higher 8-bit timer
operation)
0024H √ √ √ √ √
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 31 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0.
Remark √: Mounted
−: Not mounted