Datasheet

RL78/L12 CHAPTER 16 DMA CONTROLLER
R01UH0330EJ0200 Rev.2.00 680
Dec 13, 2013
16.2.2 DMA RAM address register n (DRAn)
This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n.
Addresses of the internal RAM area other than the general-purpose registers can be set to this register.
Set the lower 16 bits of the RAM address.
This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8-bit
transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this DRAn register.
When the data of the last address has been transferred, the DRAn register stops with the value of the last address +1 in
the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Figure 16-2. Format of DMA RAM Address Register n (DRAn)
Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRAn
(n = 0, 1)
Remark n: DMA channel number (n = 0, 1)
DRA0H: FFFB3H
DRA1H: FFFB5H
DRA0L: FFFB2H
DRA1L: FFFB4H