Datasheet

RL78/L12 CHAPTER 15 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
R01UH0330EJ0200 Rev.2.00 669
Dec 13, 2013
Notes 1. Bits 1 and 2 are read-only bits.
2. The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is
started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends.
In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to
multiplication/division data register A (MDAH, MDAL), respectively.
Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is
1). If it is rewritten, the operation result will be an undefined value.
2. The DIVST bit cannot be cleared (0) by using software during division operation processing
(while the DIVST bit is 1).
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