Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER

R01UH0330EJ0200 Rev.2.00 613

Dec 13, 2013

Figure 14-4. Format of LCD Mode Register 1 (LCDM1) (2/2)

Address: FFF41H After reset

: 00H R/W

Symbol <7> <6> <5> <4> <3> 2 1 <0>

LCDM1 LCDON SCOC VLCON BLON LCDSEL 0 0 LCDVLM

LCDVLM

Note

Control of default value of voltage boosting pin

0 Set when VDD ≥ 2.7 V

1 Set when VDD ≤ 4.2 V

Note This bit is used to boost the voltage efficiently when using the voltage boost circuit by setting the initial V

pin status.

If V

DD is 2.7 V or higher when voltage boosting starts, set the LCDVLM bit to 0; if VDD is 4.2 V or lower, set

the LCDVLM bit to 1.

If V

DD is within the range between 2.7 V and 4.2 V, the LCDVLM bit may be set to 0 or 1.

Cautions 1. To reduce power consumption when nothing is to be displayed on the LCD while the voltage

boost circuit is in use, set the SCOC and VLCON bits to “0”, and set the MDSET1 and

MDSET0 bits to “00”.

When MDSET1 and MDSET0 = 01, the internal reference voltage generator operates and so

consumes power.

2. When the external resistance division method has been set (MDSET1 and MDSET0 of LCDM0

= 00B) or capacitor split method has been set (MDSET1 and MDSET0 = 10B), set the LCDVLM

bit to 0.

3. Do not rewrite the VLCON and LCDVLM bits while SCOC = 1.

4. Set the BLON and LCDSEL bits to 0 when 8 has been selected as the number of time slices

for the display mode.

5. To use the internal voltage boosting method, specify the reference voltage by using the

VLCD register (select the internal boosting method (by setting the MDSET1 and MDSET0 bits

of the LCDM0 register to 01B) if the default reference voltage is used), wait for the reference

voltage setup time (5 ms (min.)), and then set the VLCON bit to 1.

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