Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 611
Dec 13, 2013
Figure 14-3. Format of LCD Mode Register 0 (LCDM0) (2/2)
Address: FFF40H After reset
: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDM0 MDSET1 MDSET0 LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0
LBAS1 LBAS0 LCD display bias mode selection
0 0 1/2 bias method
0 1 1/3 bias method
1 0 1/4 bias method
1 1 Setting prohibited
Cautions 1. Do not rewrite the LCDM0 value while the SCOC bit of the LCDM1 register = 1.
2. When “Static” is selected (LDTY2 to LDTY0 bits = 000B), be sure to set the LBAS1 and LBAS0
bits to the default value (00B). Otherwise, the operation will not be guaranteed.
3. Only the combinations of display waveform, number of time slices, and bias method shown in
Table 14-4 are supported.
Combinations of settings not shown in Table 14-4 are prohibited.
Tabl
e 14-4. Combinations of Display Waveform, Time Slices, and Bias Method and Frame Frequency
Display Mode Set Value Driving Voltage Generation Method
Display Waveform Number
of Time
Slices
Bias
Mode
LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0 External
Resistance
Division
Internal
Voltage
Boosting
Capacitor
Split
Waveform A 8 1/4 0 1 0 1 1 0

(24 to 128 Hz)

(24 to 64 Hz)
×
Waveform A 4 1/3 0 0 1 1 0 1

(24 to 128 Hz)

(24 to 128 Hz)

(24 to 128 Hz)
Waveform A 3 1/3 0 0 1 0 0 1

(32 to 128 Hz)

(32 to 128 Hz)

(32 to 128 Hz)
Waveform A 3 1/2 0 0 1 0 0 0

(32 to 128 Hz)
× ×
Waveform A 2 1/2 0 0 0 1 0 0

(24 to 128 Hz)
× ×
Waveform A Static 0 0 0 0 0 0

(24 to 128 Hz)
× ×
Waveform B 8 1/4 1 1 0 1 1 0

(24 to 128 Hz)

(24 to 64 Hz)
×
Waveform B 4 1/3 1 0 1 1 0 1

(24 to 128 Hz)

(24 to 128 Hz)

(24 to 128 Hz)
Remark : Supported
×: Not supported
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