Datasheet

RL78/L12 CHAPTER 14 LCD CONTROLLER/DRIVER
R01UH0330EJ0200 Rev.2.00 610
Dec 13, 2013
14.3.2 LCD mode register 0 (LCDM0)
LCDM0 specifies the LCD operation.
This register is set by using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDM0 to 00H.
Figure 14-3. Format of LCD Mode Register 0 (LCDM0) (1/2)
Address: FFF40H After reset
: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDM0 MDSET1 MDSET0 LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0
MDSET1 MDSET0 LCD drive voltage generator selection
0 0 External resistance division method
0 1 Internal voltage boosting method
1 0 Capacitor split method
1 1 Setting prohibited
LWAVE LCD display waveform selection
0 Waveform A
1 Waveform B
LDTY2 LDTY1 LDTY0 Selection of time slice of LCD display
0 0 0 Static
0 0 1 2-time slice
0 1 0 3-time slice
0 1 1 4-time slice
1 0 1 8-time slice
Other than above Setting prohibited
<R>