Datasheet

RL78/L12 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0330EJ0200 Rev.2.00 537
Dec 13, 2013
13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers
(1) Setting transfer clock on master side
Transfer clock =
f
CLK
IICWL0 + IICWH0 + fCLK (tR + tF)
At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
IICWL0 =
0.52
Transfer clock
× fCLK
IICWH0 = (
0.48
Transfer clock
− tR − tF) × fCLK
• When the normal mode
IICWL0 =
0.47
Transfer clock
× fCLK
IICWH0 = (
0.53
Transfer clock
− tR − tF) × fCLK
• When the fast mode plus
IICWL0 =
0.50
Transfer clock
× fCLK
IICWH0 = (
0.50
Transfer clock
− tR − tF) × fCLK
(2) Setting IICWL0 and IICWH0 registers on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL0 = 1.3
μ s × fCLK
IICWH0 = (1.2
μ s − tR − tF) × fCLK
• When the normal mode
IICWL0 = 4.7
μ s × fCLK
IICWH0 = (5.3
μ s − tR − tF) × fCLK
• When the fast mode plus
IICWL0 = 0.50
μ s × fCLK
IICWH0 = (0.50
μ s − tR − tF) × fCLK
(Caution and Remarks are listed on the next page.)