Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 510
Dec 13, 2013
12.7.2 LIN reception
UART0 reception supports LIN communication.
For LIN reception, channel 1 is used.
UART UART0
Support of LIN communication Supported
Target channel Channel 1
Pins used RxD0
Interrupt INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt INTSRE0
Error detection flag • Framing error detection flag (FEF01)
• Overrun error detection flag (OVF01)
Transfer data length 8 bits
Transfer rate Max. fMCK/6 [bps] (SDR01 [15:9] = 2 or more), Min. fCLK/(2 × 2
15
× 128) [bps]
Note
Data phase Non-reverse output (default: high level)
Reverse output (default: low level)
Parity bit No parity bit (The parity bit is not checked.)
Stop bit Check the first bit
Data direction LSB first
Note Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in
the electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C) and
CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: T
A = -40 to +105°C)).
Remark f
MCK: Operation clock frequency of target channel
f
CLK: System clock frequency
Figure 12-98 outlines a reception operation of LIN.