Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 500
Dec 13, 2013
Figure 12-92. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
Setting start
Does TSFmn = 0 on all
channels?
No
Yes
Writing 1 to the STmn bit
→ SEmn = 0
Entered the STOP mode
The operation of all channels is also stopped to switch to
the STOP mode.
f
CLK
supplied to the SAU is stopped.
<1>
<2>
<3>
<4>
<5>
<7>
<6>
Reading receive data from
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
<9>
<8>
Writing 1 to the STm1 bit
The mode switches from SNOOZE to normal operation.
SIRm1 = 0007H
Clear the all error flags
If an error occurs, because the CPU switches to
the STOP state again, the error flag is not set.
Channel 1 is specified for UART reception.
(EOCmn: Enable error interrupt.)
SAU default setting
Setting SSCm register
(SWCm = 1, SSECm = 1)
Writing 1 to the SSmn bit
→ SEmn = 1
SNOOZE mode setting (make the setting to enable generation
of error interrupt INTSREq in SNOOZE mode).
Communication wait status
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set interrupt disable (IE = 0).
Setting interrupt
Setting SSCm register
(SWCm = 0, SSECm = 0)
Reset SNOOZE mode setting
To operation stop status (SEm1 = 0)
RxDq edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
RxDq edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
Transfer end interrupt (INTSRq) generated
Normal operation
Normal operation
STOP mode
SNOOZE modeSTOP mode SNOOZE mode
Reception error detected
<7>
INTSRq
Change to the UART
reception baud rate in
normal operation
Writing 1 to the SSmn bit
Normal operation
Set the SPSm register and bits 15 to 9 in the SDRm1
register.
To communication wait status (SEmn = 1)
<10>
<11>
(Caution and Remarks are listed on the next page.)
<R>