Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 487
Dec 13, 2013
12.6.2 UART reception
UART reception is an operation wherein the RL78/L12 asynchronously receives data from another device (start-stop
synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the
odd- and even-numbered channels must be set.
UART UART0
Target channel Channel 1
Pins used RxD0
Interrupt INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt INTSRE0
Error detection flag • Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
Transfer data length 7, 8 or 9 bits
Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2
15
× 128) [bps]
Note
Data phase Non-reverse output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit (no parity check)
• No parity judgment (0 parity)
• Appending even parity
• Appending odd parity
Stop bit 1 bit check
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics
in the electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (A, G: T
A = -40 to +85°C)
and CHAPTER 31 ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)).
Remarks 1. f
MCK: Operation clock frequency of target channel
fCLK: System clock frequency
2. m: Unit number (m = 0), n: Channel number (n = 1), mn = 01