Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 394
Dec 13, 2013
12.3.5 Higher 7 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) function as a
transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that sets the division ratio of the
operation clock (f
MCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock by
bits 15 to 9 (higher 7 bits) of the SDRmn register is used as the transfer clock.
The lower 9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel data
converted by the shift register is stored in the lower 9 bits, and during transmission, the data to be transmitted to the shift
register is set to the lower 9 bits.
If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, set bits 15 to 9 (higher 7 bits) of SDR00, SDR01,
SDR10, and SDR11 to 0000000B. The input clock f
SCK (slave transfer in CSI mode) from the SCKp pin is used as the
transfer clock.
The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel
data converted by the shift register is stored in the lower 8/9 bits, and during transmission, the data to be transmitted to the
shift register is set to the lower 8/9 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 9 bits of the SDRmn register. When the SDRmn register is read during
operation, 0 is always read.
Reset signal generation clears the SDRmn register to 0000H.
Figure 12-7. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
SDRmn[15:9] Transfer clock setting by dividing the operating clock (fMCK)
0 0 0 0 0 0 0 fMCK/2
0 0 0 0 0 0 1 fMCK/4
0 0 0 0 0 1 0 fMCK/6
0 0 0 0 0 1 1 fMCK/8
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1 1 1 1 1 1 0 fMCK/254
1 1 1 1 1 1 1 fMCK/256
Cautions 1. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART0 is used.
2. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If
these bits are written to, the higher seven bits are cleared to 0.)
Remarks 1. For the function of the lower 9 bits of the SDRmn register, see 12.2 Configuration of Serial Array
Unit.
2. m: Unit number (m = 0), n: Channel number (n = 0, 1)
FFF11H (SDR00)
FFF10H (SDR00)
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