Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 393
Dec 13, 2013
Figure 12-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2)
Address: F0118H, F0119H (SCR00), F011AH, F011BH (SCR01) After reset: 0087H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXE
mn
RXE
mn
DAP
mn
CKP
mn
0
EOC
mn
PTC
mn1
PTC
mn0
DIR
mn
0
SLC
mn1
Note 1
SLC
mn0
0 1
DLS
mn1
DLS
mn0
PTC
mn1
PTC
mn0
Setting of parity bit in UART mode
Transmission Reception
0 0 Does not output the parity bit. Receives without parity
0 1 Outputs 0 parity
Note 2
. No parity judgment
1 0 Outputs even parity. Judged as even parity.
1 1 Outputs odd parity. Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode.
DIR
mn
Selection of data transfer sequence in CSI and UART modes
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
SLC
mn1
Note 1
SLC
mn0
Setting of stop bit in UART mode
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits (mn = 00, 02, 10, 12 only)
1 1 Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
DLS
mn1
DLS
mn0
Setting of data length in CSI and UART modes
0 1 9-bit data length (stored in bits 0 to 8 of the SDRmn register) (settable in UART0 mode only)
1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Other than above Setting prohibited
Notes 1. The SCR00 register only.
2. 0 is always added regardless of the data contents.
Caution Be sure to clear the following bits to “0”.
SCR00: bits 11, 6, 3
SCR01: bits 11, 6, 5, 3
Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01)