Datasheet

RL78/L12 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 383
Dec 13, 2013
12.2 Configuration of Serial Array Unit
The serial array unit includes the following hardware.
Table 12-1. Configuration of Serial Array Unit
Item Configuration
Shift register 9 bits
Buffer register Lower 9 bits of serial data register mn (SDRmn)
Note
Serial clock I/O SCK00, SCK01 pins (for 3-wire serial I/O)
Serial data input SI00, SI01 pins (for 3-wire serial I/O), RXD0 pin (for UART supporting LIN-bus)
Serial data output SO00, SO01 pins (for 3-wire serial I/O), TXD0 pin (for UART supporting LIN-bus), output controller
Control registers
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output register m (SOm)
• Serial output level register m (SOLm)
• Serial standby control register m (SSCm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
<Registers of each channel>
• Serial data register mn (SDRmn)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Port input mode register 1 (PIM1)
• Port output mode register 1 (POM1)
• LCD port function registers 0, 3 (PFSEG0, PFSEG3)
• Port mode register 1 (PM1)
• Port register 1 (P1)
Note The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on
the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01),
q: UART number (q = 0)