Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 378
Dec 13, 2013
Figure 11-38. Analog Input Pin Connection
AV REFP or V DD
ANI0, ANI1 and ANI16 to ANI23
Reference
voltage
input
C = 100 to 1,000 pF
If there is a possibility that noise equal to or higher than AV
REFP and
V
DD or equal to or lower than AV REFM and V SS may enter, clamp with
a diode with a small V
F value (0.3 V or lower).
(5) Analog input (ANIn) pins
<1> The analog input pins (ANI0 and ANI1) are also used as input port pins (P20 and P21). When A/D conversion
is performed with any of the ANI0 and ANI1 pins selected, do not change to output value P20 and P21 while
conversion is in progress; otherwise the conversion resolution may be degraded.
<2> If a pin adjacent to a pin that is being A/D converted is used as a digital I/O port pin, the A/D conversion result
might differ from the expected value due to a coupling noise. Be sure to avoid the input or output of digital
signals and signals with similarly sharp transitions during conversion.
(6) Input impedance of analog input (ANIn) pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor
flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress,
and on the other states.
To make sure that sampling is effective, however, we recommend using the converter with analog input sources that
have output impedances no greater than 1 kΩ. If a source has a higher output impedance, lengthen the sampling
time or connect a larger capacitor (with a value of about 0.1
μ F) to the pin from among ANI0, ANI1, and ANI16 to
ANI23 to which the source is connected (see Figure 11-38). The sampling capacitor may be being charged while the
setting of the ADCS bit is 0 and immediately after sampling is restarted and so is not defined at these times.
Accordingly, the state of conversion is undefined after charging starts in the next round of conversion after the value
of the ADCS bit has been 1 or when conversion is repeated. Thus, to secure full charging regardless of the size of
fluctuations in the analog signal, ensure that the output impedances of the sources of analog inputs are low or secure
sufficient time for the completion of conversion.
(7) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the
pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this
time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
<R>
<R>