Datasheet
RL78/L12 CHAPTER 1 OUTLINE
R01UH0330EJ0200 Rev.2.00 18
Dec 13, 2013
(2/2)
Item 32-pin 44-pin 48-pin 52-pin 64-pin
R5F10RBx R5F10RFx R5F10RGx R5F10RJx R5F10RLx
Timer 16-bit timer 8 channels 8 channels (with 1 channel remote control output function)
Watchdog timer 1 channel
Real-time clock (RTC) 1 channel
12-bit interval timer (IT) 1 channel
Timer output 4 channels
(PWM outputs:
3
Note 1
)
5 channels
(PWM outputs:
4
Note 1
)
6 channels
(PWM outputs:
5
Note 1
)
8 channels (PWM outputs: 7
Note 1
)
RTC output
−
1
• 1 Hz (subsystem clock: f
SUB = 32.768 kHz or )
Clock output/buzzer output 1 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f
MAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,
32.768 kHz
(Subsystem clock: f
SUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 4 channels 7 channels 9 channels 10 channels 10 channels
Serial interface • CSI: 2 channel/UART (LIN-bus supported): 1 channel
I
2
C bus
1 channel 1 channel 1 channel 1 channel 1 channel
Multiplier and divider/multiply-
accumulator
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller 2 channels
Vectored interrupt
sources
Internal 23 23 23 23 23
External 4 6 7 7 9
Key interrupt 4
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset: 1.51 ±0.04 V
• Power-down-reset: 1.50 ±0.04 V
Voltage detector
• Rising edge : 1.67 V to 4.06 V (14 stages)
• Falling edge : 1.63 V to 3.98 V (14 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = −40 to +85 °C
Notes 1. The number of PWM outputs varies depending on the setting of channels in use (the number of masters
and slaves). (6.9.3 Operation as multiple PWM output function)
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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